fixes for DataMerger

[soc.git] / src / soc / experiment / l0_cache.py

diff --git a/src/soc/experiment/l0_cache.py b/src/soc/experiment/l0_cache.py
index e9fdfcd80a32abf72de8e48399f82765ede953ad..351d09cc849a8df754ec7cdfb9521f15bb27ea91 100644 (file)
--- a/src/soc/experiment/l0_cache.py
+++ b/src/soc/experiment/l0_cache.py
@@ -25,6 +25,8 @@ from nmigen.hdl.rec import Record, Layout
 from nmutil.latch import SRLatch, latchregister
 from soc.decoder.power_decoder2 import Data
 from soc.decoder.power_enums import InternalOp
+from soc.regfile.regfile import ortreereduce
+from nmutil.util import treereduce
 
 from soc.experiment.compldst import CompLDSTOpSubset
 from soc.decoder.power_decoder2 import Data
@@ -34,7 +36,6 @@ from nmigen.lib.coding import PriorityEncoder
 # for testing purposes
 from soc.experiment.testmem import TestMemory
 
-
 class PortInterface(RecordObject):
     """PortInterface
 
@@ -143,14 +144,15 @@ class DataMergerRecord(Record):
 
         Record.__init__(self, Layout(layout), name=name)
 
-# TODO:
+        #FIXME: make resetless
 
+# TODO: unit test
 
 class DataMerger(Elaboratable):
     """DataMerger
 
-    Merges data based on an address-match matrix.  
-    Identifies (picks) one (any) row, then uses that row, 
+    Merges data based on an address-match matrix.
+    Identifies (picks) one (any) row, then uses that row,
     based on matching address bits, to merge (OR) all data
     rows into the output.
 
@@ -190,22 +192,28 @@ class DataMerger(Elaboratable):
         self.data_i = Array(ul)
         self.data_o = DataMergerRecord()
 
-        def elaborate(self, platform):
-            m = Module()
-            comb, sync = m.d.comb, m.d.sync
-            #(1) pick a row
-            m.submodules.pick = pick = PriorityEncoder(self.array_size)
-            pick.i.eq(0)
-            for j in range(self.addr):
-                with m.If(self.addr_match_i[j]>0):
-                    pick.i.eq(pick.i||(1<<j))
-            valid = ~pick.n
-            idx = pick.o
-            #(2) merge
-            self.data_o.eq(0)
+    def elaborate(self, platform):
+        m = Module()
+        comb = m.d.comb
+        #(1) pick a row
+        m.submodules.pick = pick = PriorityEncoder(self.array_size)
+        for j in range(self.array_size):
+            comb += pick.i[j].eq(self.addr_array_i[j].bool())
+        valid = ~pick.n
+        idx = pick.o
+        #(2) merge
+        with m.If(valid):
+            l = []
             for j in range(self.array_size):
-                with m.If(self.addr_match_i[idx][j] && valid):
-                    self.data_o.eq(self.data_i[j]|self.data_o)
+                select = self.addr_array_i[idx][j]
+                r = DataMergerRecord()
+                with m.If(select):
+                    comb += r.eq(self.data_i[j])
+                l.append(r)
+            comb += self.data_o.data.eq(ortreereduce(l,"data"))
+            comb += self.data_o.en.eq(ortreereduce(l,"en"))
+
+        return m
 
 
 class LDSTPort(Elaboratable):
@@ -521,6 +529,9 @@ def l0_cache_ldst(dut):
     assert data == result, "data %x != %x" % (result, data)
     assert data2 == result2, "data2 %x != %x" % (result2, data2)
 
+def data_merger_merge(dut):
+    print("TODO")
+    yield
 
 def test_l0_cache():
 
@@ -532,6 +543,17 @@ def test_l0_cache():
     run_simulation(dut, l0_cache_ldst(dut),
                    vcd_name='test_l0_cache_basic.vcd')
 
+def test_data_merger():
+
+    dut = DataMerger(8)
+    #vl = rtlil.convert(dut, ports=dut.ports())
+    #with open("test_data_merger.il", "w") as f:
+    #    f.write(vl)
+
+    run_simulation(dut, data_merger_merge(dut),
+                   vcd_name='test_data_merger.vcd')
+
 
 if __name__ == '__main__':
     test_l0_cache()
+    #test_data_merger()