unit test for DataMerger

[soc.git] / src / soc / experiment / l0_cache.py

diff --git a/src/soc/experiment/l0_cache.py b/src/soc/experiment/l0_cache.py
index 40e73a3d9921dc499ca45a017299c93cfc0d784c..3e2c453c5a936a1e8b51ae914e14d1d3559f1da7 100644 (file)
--- a/src/soc/experiment/l0_cache.py
+++ b/src/soc/experiment/l0_cache.py
@@ -26,6 +26,7 @@ from nmutil.latch import SRLatch, latchregister
 from soc.decoder.power_decoder2 import Data
 from soc.decoder.power_enums import InternalOp
 from soc.regfile.regfile import ortreereduce
+from nmutil.util import treereduce
 
 from soc.experiment.compldst import CompLDSTOpSubset
 from soc.decoder.power_decoder2 import Data
@@ -143,13 +144,15 @@ class DataMergerRecord(Record):
 
         Record.__init__(self, Layout(layout), name=name)
 
-# TODO: unit test
+        #FIXME: make resetless
+
+# TODO: formal verification
 
 class DataMerger(Elaboratable):
     """DataMerger
 
-    Merges data based on an address-match matrix.  
-    Identifies (picks) one (any) row, then uses that row, 
+    Merges data based on an address-match matrix.
+    Identifies (picks) one (any) row, then uses that row,
     based on matching address bits, to merge (OR) all data
     rows into the output.
 
@@ -189,22 +192,28 @@ class DataMerger(Elaboratable):
         self.data_i = Array(ul)
         self.data_o = DataMergerRecord()
 
-        def elaborate(self, platform):
-            m = Module()
-            comb = m.d.comb
-            #(1) pick a row
-            m.submodules.pick = pick = PriorityEncoder(self.array_size)
+    def elaborate(self, platform):
+        m = Module()
+        comb = m.d.comb
+        #(1) pick a row
+        m.submodules.pick = pick = PriorityEncoder(self.array_size)
+        for j in range(self.array_size):
+            comb += pick.i[j].eq(self.addr_array_i[j].bool())
+        valid = ~pick.n
+        idx = pick.o
+        #(2) merge
+        with m.If(valid):
+            l = []
             for j in range(self.array_size):
-                comb += pick.i[j].eq(self.addr_match_i[j].bool())
-            valid = ~pick.n
-            idx = pick.o
-            #(2) merge
-            with m.If(valid):
-                l = []
-                for j in range(self.array_size):
-                    select = self.addr_match_i[idx][j]
-                    l.append(Mux(select, self.data_i[j], 0))
-                comb += self.data_o.eq(ortreereduce(l))
+                select = self.addr_array_i[idx][j]
+                r = DataMergerRecord()
+                with m.If(select):
+                    comb += r.eq(self.data_i[j])
+                l.append(r)
+            comb += self.data_o.data.eq(ortreereduce(l,"data"))
+            comb += self.data_o.en.eq(ortreereduce(l,"en"))
+
+        return m
 
 
 class LDSTPort(Elaboratable):
@@ -521,7 +530,22 @@ def l0_cache_ldst(dut):
     assert data2 == result2, "data2 %x != %x" % (result2, data2)
 
 def data_merger_merge(dut):
-    print("TODO")
+    print("data_merger")
+    #starting with all inputs zero
+    en = yield dut.data_o.en
+    data = yield dut.data_o.data
+    assert en == 0, "en must be zero"
+    assert data == 0, "data must be zero"
+    yield
+    yield dut.addr_array_i[0].eq(0xFF)
+    for j in range(dut.array_size):
+        yield dut.data_i[j].en.eq(1 << j)
+        yield dut.data_i[j].data.eq(0xFF << (16*j))
+    yield
+    en = yield dut.data_o.en
+    data = yield dut.data_o.data
+    assert data == 0xff00ff00ff00ff00ff00ff00ff00ff
+    assert en == 0xff
     yield
 
 def test_l0_cache():
@@ -547,4 +571,4 @@ def test_data_merger():
 
 if __name__ == '__main__':
     test_l0_cache()
-    #test_data_merger()
+    test_data_merger()