from nmigen.hdl.rec import Record, Layout
from nmutil.latch import SRLatch, latchregister
-from soc.decoder.power_decoder2 import Data
-from soc.decoder.power_enums import MicrOp
+from openpower.decoder.power_decoder2 import Data
+from openpower.decoder.power_enums import MicrOp
from soc.regfile.regfile import ortreereduce
from nmutil.util import treereduce
-from soc.decoder.power_decoder2 import Data
+from openpower.decoder.power_decoder2 import Data
#from nmutil.picker import PriorityPicker
from nmigen.lib.coding import PriorityEncoder
from soc.scoreboard.addr_split import LDSTSplitter
from soc.config.test.test_pi2ls import pi_ld, pi_st, pi_ldst
import unittest
+class L0CacheBuffer2(Elaboratable):
+ """L0CacheBuffer2"""
+ def __init__(self, n_units=8, regwid=64, addrwid=48):
+ self.n_units = n_units
+ self.regwid = regwid
+ self.addrwid = addrwid
+ ul = []
+ for i in range(self.n_units):
+ ul += [PortInterface()]
+ self.dports = Array(ul)
-class DualPortSplitter(Elaboratable):
- """DualPortSplitter
-
- * one incoming PortInterface
- * two *OUTGOING* PortInterfaces
- * uses LDSTSplitter to do it
-
- (actually, thinking about it LDSTSplitter could simply be
- modified to conform to PortInterface: one in, two out)
-
- once that is done each pair of ports may be wired directly
- to the dual ports of L0CacheBuffer
-
- The split is carried out so that, regardless of alignment or
- mis-alignment, outgoing PortInterface[0] takes bit 4 == 0
- of the address, whilst outgoing PortInterface[1] takes
- bit 4 == 1.
+ def elaborate(self, platform):
+ m = Module()
+ comb, sync = m.d.comb, m.d.sync
- PortInterface *may* need to be changed so that the length is
- a binary number (accepting values 1-16).
- """
+ # connect the ports as modules
- def __init__(self):
- self.outp = [PortInterface(name="outp_0"),
- PortInterface(name="outp_1")]
- self.inp = PortInterface(name="inp")
- print(self.outp)
+ for i in range(self.n_units):
+ d = LDSTSplitter(64, 48, 4, self.dports[i])
+ setattr(m.submodules, "ldst_splitter%d" % i, d)
- def elaborate(self, platform):
- m = Module()
- comb = m.d.comb
- m.submodules.splitter = splitter = LDSTSplitter(64, 48, 4)
- comb += splitter.addr_i.eq(self.inp.addr) # XXX
- #comb += splitter.len_i.eq()
- #comb += splitter.valid_i.eq()
- comb += splitter.is_ld_i.eq(self.inp.is_ld_i)
- comb += splitter.is_st_i.eq(self.inp.is_st_i)
- #comb += splitter.st_data_i.eq()
- #comb += splitter.sld_valid_i.eq()
- #comb += splitter.sld_data_i.eq()
- #comb += splitter.sst_valid_i.eq()
+ # state-machine latches TODO
return m
-
class DataMergerRecord(Record):
"""
{data: 128 bit, byte_enable: 16 bit}
ul.append(CacheRecord())
self.input_array = Array(ul)
+ def addr_match(self,j,addr):
+ ret = []
+ for k in range(self.n_units):
+ ret += [(addr[j] == addr[k])]
+ return Cat(*ret)
+
def elaborate(self, platform):
m = Module()
m.submodules.dm_odd = dm_odd = DataMerger(self.n_units)
m.submodules.dm_even = dm_even = DataMerger(self.n_units)
- #TODO assign data and address match
- #m.d.comb += dm_even.addr_array_i.eq(TODO)
- #m.d.comb += dm_odd.addr_array_i.eq(TODO)
- #m.d.comb += dm_even.data_i.eq(TODO)
- #m.d.comb += dm_odd.data_i.eq(TODO)
+ addr_even = []
+ addr_odd = []
+ for j in range(self.n_units):
+ inp = self.input_array[j]
+ addr_even += [Cat(inp.addr,inp.a_even)]
+ addr_odd += [Cat(inp.addr,inp.a_odd)]
+
+ for j in range(self.n_units):
+ inp = self.input_array[j]
+ m.d.comb += dm_even.data_i[j].en.eq(inp.bytemask_even)
+ m.d.comb += dm_odd.data_i[j].en.eq(inp.bytemask_odd)
+ m.d.comb += dm_even.data_i[j].data.eq(inp.data_even)
+ m.d.comb += dm_odd.data_i[j].data.eq(inp.data_odd)
+ m.d.comb += dm_even.addr_array_i[j].eq(self.addr_match(j,addr_even))
+ m.d.comb += dm_odd.addr_array_i[j].eq(self.addr_match(j,addr_odd))
m.d.comb += self.data_odd.eq(dm_odd.data_o.data)
m.d.comb += self.data_even.eq(dm_even.data_o.data)
- self.data
return m
class TstL0CacheBuffer(Elaboratable):
def __init__(self, pspec, n_units=3):
+ self.pspec = pspec
regwid = pspec.reg_wid
addrwid = pspec.addr_wid
self.cmpi = ConfigMemoryPortInterface(pspec)
m = Module()
m.submodules.pimem = self.pimem
m.submodules.l0 = self.l0
- if hasattr(self.cmpi, 'lsmem'): # hmmm not happy about this
- m.submodules.lsmem = self.cmpi.lsmem.lsi
+
+ if not hasattr(self.cmpi, 'lsmem'):
+ return m
+
+ # really bad hack, the LoadStore1 classes already have the
+ # lsi (LoadStoreInterface) as a submodule.
+ if self.pspec.ldst_ifacetype in ['mmu_cache_wb', 'test_mmu_cache_wb']:
+ return m
+
+ # hmmm not happy about this - should not be digging down and
+ # putting modules in
+ m.submodules.lsmem = self.cmpi.lsmem.lsi
return m
def data_merger_merge(dut):
- print("data_merger")
# starting with all inputs zero
yield Settle()
en = yield dut.data_o.en
assert en == 0xff
yield
+def data_merger_test2(dut):
+ # starting with all inputs zero
+ yield Settle()
+ yield
+ yield
+
class TestL0Cache(unittest.TestCase):
def test_data_merger(self):
- dut = DataMerger(8)
+ dut = TstDataMerger2()
#vl = rtlil.convert(dut, ports=dut.ports())
# with open("test_data_merger.il", "w") as f:
# f.write(vl)
- run_simulation(dut, data_merger_merge(dut),
+ run_simulation(dut, data_merger_test2(dut),
vcd_name='test_data_merger.vcd')
+
class TestDualPortSplitter(unittest.TestCase):
def test_dual_port_splitter(self):
projects / soc.git / blobdiff