test_ldst_pi.py: first version of test_dcache_random()

[soc.git] / src / soc / experiment / l0_cache.py

diff --git a/src/soc/experiment/l0_cache.py b/src/soc/experiment/l0_cache.py
index 81ebd9301fefcbf4184782ccd03a1559eef43d54..8414f77f75631691df9c358646fac454de950040 100644 (file)
--- a/src/soc/experiment/l0_cache.py
+++ b/src/soc/experiment/l0_cache.py
@@ -23,12 +23,12 @@ from nmigen.utils import log2_int
 from nmigen.hdl.rec import Record, Layout
 
 from nmutil.latch import SRLatch, latchregister
-from soc.decoder.power_decoder2 import Data
-from soc.decoder.power_enums import MicrOp
+from openpower.decoder.power_decoder2 import Data
+from openpower.decoder.power_enums import MicrOp
 from soc.regfile.regfile import ortreereduce
 from nmutil.util import treereduce
 
-from soc.decoder.power_decoder2 import Data
+from openpower.decoder.power_decoder2 import Data
 #from nmutil.picker import PriorityPicker
 from nmigen.lib.coding import PriorityEncoder
 from soc.scoreboard.addr_split import LDSTSplitter
@@ -41,51 +41,30 @@ from soc.experiment.pimem import PortInterface
 from soc.config.test.test_pi2ls import pi_ld, pi_st, pi_ldst
 import unittest
 
+class L0CacheBuffer2(Elaboratable):
+    """L0CacheBuffer2"""
+    def __init__(self, n_units=8, regwid=64, addrwid=48):
+        self.n_units = n_units
+        self.regwid = regwid
+        self.addrwid = addrwid
+        ul = []
+        for i in range(self.n_units):
+            ul += [PortInterface()]
+        self.dports = Array(ul)
 
-class DualPortSplitter(Elaboratable):
-    """DualPortSplitter
-
-    * one incoming PortInterface
-    * two *OUTGOING* PortInterfaces
-    * uses LDSTSplitter to do it
-
-    (actually, thinking about it LDSTSplitter could simply be
-     modified to conform to PortInterface: one in, two out)
-
-    once that is done each pair of ports may be wired directly
-    to the dual ports of L0CacheBuffer
-
-    The split is carried out so that, regardless of alignment or
-    mis-alignment, outgoing PortInterface[0] takes bit 4 == 0
-    of the address, whilst outgoing PortInterface[1] takes
-    bit 4 == 1.
+    def elaborate(self, platform):
+        m = Module()
+        comb, sync = m.d.comb, m.d.sync
 
-    PortInterface *may* need to be changed so that the length is
-    a binary number (accepting values 1-16).
-    """
+        # connect the ports as modules
 
-    def __init__(self):
-        self.outp = [PortInterface(name="outp_0"),
-                     PortInterface(name="outp_1")]
-        self.inp = PortInterface(name="inp")
-        print(self.outp)
+        for i in range(self.n_units):
+            d = LDSTSplitter(64, 48, 4, self.dports[i])
+            setattr(m.submodules, "ldst_splitter%d" % i, d)
 
-    def elaborate(self, platform):
-        m = Module()
-        comb = m.d.comb
-        m.submodules.splitter = splitter = LDSTSplitter(64, 48, 4)
-        comb += splitter.addr_i.eq(self.inp.addr)  # XXX
-        #comb += splitter.len_i.eq()
-        #comb += splitter.valid_i.eq()
-        comb += splitter.is_ld_i.eq(self.inp.is_ld_i)
-        comb += splitter.is_st_i.eq(self.inp.is_st_i)
-        #comb += splitter.st_data_i.eq()
-        #comb += splitter.sld_valid_i.eq()
-        #comb += splitter.sld_data_i.eq()
-        #comb += splitter.sst_valid_i.eq()
+        # state-machine latches TODO
         return m
 
-
 class DataMergerRecord(Record):
     """
     {data: 128 bit, byte_enable: 16 bit}
@@ -330,6 +309,7 @@ class L0CacheBuffer(Elaboratable):
 
 class TstL0CacheBuffer(Elaboratable):
     def __init__(self, pspec, n_units=3):
+        self.pspec = pspec
         regwid = pspec.reg_wid
         addrwid = pspec.addr_wid
         self.cmpi = ConfigMemoryPortInterface(pspec)
@@ -340,8 +320,18 @@ class TstL0CacheBuffer(Elaboratable):
         m = Module()
         m.submodules.pimem = self.pimem
         m.submodules.l0 = self.l0
-        if hasattr(self.cmpi, 'lsmem'):  # hmmm not happy about this
-            m.submodules.lsmem = self.cmpi.lsmem.lsi
+
+        if not hasattr(self.cmpi, 'lsmem'):
+            return m
+
+        # really bad hack, the LoadStore1 classes already have the
+        # lsi (LoadStoreInterface) as a submodule.
+        if self.pspec.ldst_ifacetype in ['mmu_cache_wb', 'test_mmu_cache_wb']:
+            return m
+
+        # hmmm not happy about this - should not be digging down and
+        # putting modules in
+        m.submodules.lsmem = self.cmpi.lsmem.lsi
 
         return m