add bare wishbone option to TestIssuer, sort out ports

[soc.git] / src / soc / experiment / l0_cache.py

diff --git a/src/soc/experiment/l0_cache.py b/src/soc/experiment/l0_cache.py
index aac034d79c990d18507d88c53d5f23b192d3e4ba..c622ef44996fd9bb533b47c6b3f163685360b62a 100644 (file)
--- a/src/soc/experiment/l0_cache.py
+++ b/src/soc/experiment/l0_cache.py
@@ -281,8 +281,9 @@ class TstL0CacheBuffer(Elaboratable):
         return m
 
     def ports(self):
+        yield from self.cmpi.ports()
         yield from self.l0.ports()
-        yield from self.pimem
+        yield from self.pimem.ports()
 
 
 def wait_busy(port, no=False):