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[soc.git] / src / soc / experiment / mem_types.py

diff --git a/src/soc/experiment/mem_types.py b/src/soc/experiment/mem_types.py
index c0feb1e3d8f6a3074c16fc258c7d741653ab4bbc..42618a237fb7827e9fc4337eb991df8474b7fab8 100644 (file)
--- a/src/soc/experiment/mem_types.py
+++ b/src/soc/experiment/mem_types.py
@@ -8,23 +8,24 @@ from nmigen import Signal
 
 
 class DCacheToLoadStore1Type(RecordObject):
-    def __init__(self):
-        super().__init__()
+    def __init__(self, name=None):
+        super().__init__(name=name)
         self.valid         = Signal()
-        self.data          = Signal()
+        self.data          = Signal(64)
         self.store_done    = Signal()
         self.error         = Signal()
         self.cache_paradox = Signal()
 
 
 class DCacheToMMUType(RecordObject):
-    def __init__(self):
-        super().__init__()
+    def __init__(self, name=None):
+        super().__init__(name=name)
         self.stall         = Signal()
         self.done          = Signal()
         self.err           = Signal()
         self.data          = Signal(64)
 
+
 class Fetch1ToICacheType(RecordObject):
     def __init__(self):
         super().__init__()
@@ -35,6 +36,7 @@ class Fetch1ToICacheType(RecordObject):
         self.sequential    = Signal()
         self.nia           = Signal(64)
 
+
 class ICacheToDecode1Type(RecordObject):
     def __init__(self):
         super().__init__()
@@ -44,20 +46,21 @@ class ICacheToDecode1Type(RecordObject):
         self.nia           = Signal(64)
         self.insn          = Signal(32)
 
+
 class LoadStore1ToDCacheType(RecordObject):
-    def __init__(self):
-        super().__init__()
+    def __init__(self, name=None):
+        super().__init__(name=name)
         self.valid         = Signal()
         self.load          = Signal() # this is a load
         self.dcbz          = Signal()
         self.nc            = Signal()
-        self.nc            = Signal()
         self.reserve       = Signal()
         self.virt_mode     = Signal()
         self.priv_mode     = Signal()
-        self.addr          = Signal()
-        self.data          = Signal()
-        self.byte_sel      = Signal()
+        self.addr          = Signal(64)
+        self.data          = Signal(64)
+        self.byte_sel      = Signal(8)
+
 
 class LoadStore1ToMMUType(RecordObject):
     def __init__(self):
@@ -73,6 +76,7 @@ class LoadStore1ToMMUType(RecordObject):
         self.addr          = Signal(64)
         self.rs            = Signal(64)
 
+
 class MMUToLoadStore1Type(RecordObject):
     def __init__(self):
         super().__init__()
@@ -85,9 +89,10 @@ class MMUToLoadStore1Type(RecordObject):
         self.rc_error      = Signal()
         self.sprval        = Signal(64)
 
+
 class MMUToDCacheType(RecordObject):
-    def __init__(self):
-        super().__init__()
+    def __init__(self, name=None):
+        super().__init__(name=name)
         self.valid         = Signal()
         self.tlbie         = Signal()
         self.doall         = Signal()
@@ -95,6 +100,7 @@ class MMUToDCacheType(RecordObject):
         self.addr          = Signal(64)
         self.pte           = Signal(64)
 
+
 class MMUToICacheType(RecordObject):
     def __init__(self):
         super().__init__()