test_ldst_pi.py: add dcache regression and random test from test_dcache.py

[soc.git] / src / soc / experiment / mem_types.py

diff --git a/src/soc/experiment/mem_types.py b/src/soc/experiment/mem_types.py
index 42618a237fb7827e9fc4337eb991df8474b7fab8..e85886b6562422258e497c0022ad6f40d081d931 100644 (file)
--- a/src/soc/experiment/mem_types.py
+++ b/src/soc/experiment/mem_types.py
@@ -6,6 +6,8 @@ based on Anton Blanchard microwatt common.vhdl
 from nmutil.iocontrol import RecordObject
 from nmigen import Signal
 
+from openpower.exceptions import LDSTException
+
 
 class DCacheToLoadStore1Type(RecordObject):
     def __init__(self, name=None):
@@ -27,8 +29,8 @@ class DCacheToMMUType(RecordObject):
 
 
 class Fetch1ToICacheType(RecordObject):
-    def __init__(self):
-        super().__init__()
+    def __init__(self, name=None):
+        super().__init__(name=name)
         self.req           = Signal()
         self.virt_mode     = Signal()
         self.priv_mode     = Signal()
@@ -38,8 +40,8 @@ class Fetch1ToICacheType(RecordObject):
 
 
 class ICacheToDecode1Type(RecordObject):
-    def __init__(self):
-        super().__init__()
+    def __init__(self, name=None):
+        super().__init__(name=name)
         self.valid         = Signal()
         self.stop_mark     = Signal()
         self.fetch_failed  = Signal()
@@ -51,20 +53,23 @@ class LoadStore1ToDCacheType(RecordObject):
     def __init__(self, name=None):
         super().__init__(name=name)
         self.valid         = Signal()
+        self.hold          = Signal()
         self.load          = Signal() # this is a load
         self.dcbz          = Signal()
         self.nc            = Signal()
         self.reserve       = Signal()
+        self.atomic        = Signal() # part of a multi-transfer atomic op
+        self.atomic_last   = Signal()
         self.virt_mode     = Signal()
         self.priv_mode     = Signal()
         self.addr          = Signal(64)
-        self.data          = Signal(64)
+        self.data          = Signal(64) # valid the cycle after valid=1
         self.byte_sel      = Signal(8)
 
 
 class LoadStore1ToMMUType(RecordObject):
-    def __init__(self):
-        super().__init__()
+    def __init__(self, name=None):
+        super().__init__(name=name)
         self.valid         = Signal()
         self.tlbie         = Signal()
         self.slbia         = Signal()
@@ -78,8 +83,8 @@ class LoadStore1ToMMUType(RecordObject):
 
 
 class MMUToLoadStore1Type(RecordObject):
-    def __init__(self):
-        super().__init__()
+    def __init__(self, name=None):
+        super().__init__(name=name)
         self.done          = Signal()
         self.err           = Signal()
         self.invalid       = Signal()
@@ -102,8 +107,8 @@ class MMUToDCacheType(RecordObject):
 
 
 class MMUToICacheType(RecordObject):
-    def __init__(self):
-        super().__init__()
+    def __init__(self, name=None):
+        super().__init__(name=name)
         self.tlbld         = Signal()
         self.tlbie         = Signal()
         self.doall         = Signal()