test_ldst_pi.py: add dcache regression and random test from test_dcache.py

[soc.git] / src / soc / experiment / mem_types.py

diff --git a/src/soc/experiment/mem_types.py b/src/soc/experiment/mem_types.py
index c0523483108030d0b8594fa6695f6ab9e7216943..e85886b6562422258e497c0022ad6f40d081d931 100644 (file)
--- a/src/soc/experiment/mem_types.py
+++ b/src/soc/experiment/mem_types.py
@@ -6,15 +6,7 @@ based on Anton Blanchard microwatt common.vhdl
 from nmutil.iocontrol import RecordObject
 from nmigen import Signal
 
-# https://bugs.libre-soc.org/show_bug.cgi?id=465
-class LDSTException(RecordObject):
-    _exc_types = ['alignment', 'instr_fault', 'invalid', 'badtree',
-                 'perm_error', 'rc_error', 'segment_fault',]
-    def __init__(self, name=None):
-        RecordObject.__init__(self, name=name)
-        self.happened = Signal()
-        for f in self._exc_types:
-            setattr(self, f, Signal())
+from openpower.exceptions import LDSTException
 
 
 class DCacheToLoadStore1Type(RecordObject):
@@ -61,14 +53,17 @@ class LoadStore1ToDCacheType(RecordObject):
     def __init__(self, name=None):
         super().__init__(name=name)
         self.valid         = Signal()
+        self.hold          = Signal()
         self.load          = Signal() # this is a load
         self.dcbz          = Signal()
         self.nc            = Signal()
         self.reserve       = Signal()
+        self.atomic        = Signal() # part of a multi-transfer atomic op
+        self.atomic_last   = Signal()
         self.virt_mode     = Signal()
         self.priv_mode     = Signal()
         self.addr          = Signal(64)
-        self.data          = Signal(64)
+        self.data          = Signal(64) # valid the cycle after valid=1
         self.byte_sel      = Signal(8)