whoops, combinatorial loop on pending_priority

[soc.git] / src / soc / experiment / pimem.py

diff --git a/src/soc/experiment/pimem.py b/src/soc/experiment/pimem.py
index 279e8971f44a9b626ed28114332ad457b2581577..3fac8cb649354b110779a250ee71935106065240 100644 (file)
--- a/src/soc/experiment/pimem.py
+++ b/src/soc/experiment/pimem.py
@@ -22,11 +22,14 @@ from nmutil.iocontrol import RecordObject
 from nmigen.utils import log2_int
 
 from nmutil.latch import SRLatch, latchregister
+from nmutil.util import rising_edge
 from soc.decoder.power_decoder2 import Data
 from soc.scoreboard.addr_match import LenExpand
 
 # for testing purposes
 from soc.experiment.testmem import TestMemory
+#from soc.scoreboard.addr_split import LDSTSplitter
+
 
 import unittest
 
@@ -166,7 +169,10 @@ class PortInterfaceBase(Elaboratable):
         m.submodules.adrok_l = adrok_l = SRLatch(False, name="addr_acked")
         m.submodules.busy_l = busy_l = SRLatch(False, name="busy")
         m.submodules.cyc_l = cyc_l = SRLatch(True, name="cyc")
-        comb += st_done.s.eq(0)
+
+        self.busy_l = busy_l
+
+        sync += st_done.s.eq(0)
         comb += st_done.r.eq(0)
         comb += st_active.r.eq(0)
         comb += ld_active.r.eq(0)
@@ -193,8 +199,8 @@ class PortInterfaceBase(Elaboratable):
         comb += busy_edge.eq(pi.busy_o & ~busy_delay)
 
         # activate mode: only on "edge"
-        comb += ld_active.s.eq(lds & busy_edge)  # activate LD mode
-        comb += st_active.s.eq(sts & busy_edge)  # activate ST mode
+        comb += ld_active.s.eq(rising_edge(m, lds))  # activate LD mode
+        comb += st_active.s.eq(rising_edge(m, sts))  # activate ST mode
 
         # LD/ST requested activates "busy" (only if not already busy)
         with m.If(self.pi.is_ld_i | self.pi.is_st_i):
@@ -249,7 +255,7 @@ class PortInterfaceBase(Elaboratable):
             # TODO: replace with link to LoadStoreUnitInterface.x_store_data
             # and also handle the ready/stall/busy protocol
             stok = self.set_wr_data(m, stdata, lenexp.lexp_o)
-            comb += st_done.s.eq(1)     # store done trigger
+            sync += st_done.s.eq(1)     # store done trigger
         with m.If(st_done.q):
             comb += reset_l.s.eq(stok)   # reset mode after 1 cycle