RecordObject.__init__(self, name=name)
- # distinguish op type (ld/st/dcbz)
+ # distinguish op type (ld/st)
self.is_ld_i = Signal(reset_less=True)
self.is_st_i = Signal(reset_less=True)
- self.is_dcbz_i = Signal(reset_less=True)
# LD/ST data length (TODO: other things may be needed)
self.data_len = Signal(4, reset_less=True)
# addr is valid (TLB, L1 etc.)
self.addr_ok_o = Signal(reset_less=True)
self.exc_o = LDSTException("exc")
+ self.dar_o = Signal(64, reset_less=True)
# LD/ST
self.ld = Data(regwid, "ld_data_o") # ok to be set by L0 Cache/Buf
# additional "modes"
self.is_nc = Signal() # no cacheing
self.msr_pr = Signal() # 1==virtual, 0==privileged
+ self.is_dcbz_i = Signal(reset_less=True)
# mmu
self.mmu_done = Signal() # keep for now
inport.busy_o.eq(self.busy_o),
inport.addr_ok_o.eq(self.addr_ok_o),
inport.exc_o.eq(self.exc_o),
+ inport.dar_o.eq(self.dar_o),
inport.mmu_done.eq(self.mmu_done),
inport.ldst_error.eq(self.ldst_error),
inport.cache_paradox.eq(self.cache_paradox)
def connect_port(self, inport):
return self.pi.connect_port(inport)
- def set_wr_addr(self, m, addr, mask, misalign, msr_pr): pass
+ def set_wr_addr(self, m, addr, mask, misalign, msr_pr, is_dcbz): pass
def set_rd_addr(self, m, addr, mask, misalign, msr_pr): pass
def set_wr_data(self, m, data, wen): pass
def get_rd_data(self, m): pass
- def set_dcbz_addr(self, m, addr): pass
def elaborate(self, platform):
m = Module()
m.submodules.st_active = st_active = SRLatch(False, name="st_active")
m.submodules.st_done = st_done = SRLatch(False, name="st_done")
m.submodules.ld_active = ld_active = SRLatch(False, name="ld_active")
- dcbz_active = SRLatch(False, name="dcbz_active")
- m.submodules.dcbz_active = dcbz_active # this one is new and untested
m.submodules.reset_l = reset_l = SRLatch(True, name="reset")
m.submodules.adrok_l = adrok_l = SRLatch(False, name="addr_acked")
m.submodules.busy_l = busy_l = SRLatch(False, name="busy")
self.busy_l = busy_l
- comb += Display("PortInterfaceBase dcbz_active.q=%i",dcbz_active.q)
-
sync += st_done.s.eq(0)
comb += st_done.r.eq(0)
comb += st_active.r.eq(0)
comb += ld_active.r.eq(0)
- comb += dcbz_active.r.eq(0)
comb += cyc_l.s.eq(0)
comb += cyc_l.r.eq(0)
comb += busy_l.s.eq(0)
lds = Signal(reset_less=True)
sts = Signal(reset_less=True)
- dcbzs = Signal(reset_less=True)
pi = self.pi
comb += lds.eq(pi.is_ld_i) # ld-req signals
comb += sts.eq(pi.is_st_i) # st-req signals
- comb += dcbzs.eq(pi.is_dcbz_i) # dcbz-req signals (new, untested)
pr = pi.msr_pr # MSR problem state: PR=1 ==> virt, PR==0 ==> priv
# detect busy "edge"
# activate mode: only on "edge"
comb += ld_active.s.eq(rising_edge(m, lds)) # activate LD mode
comb += st_active.s.eq(rising_edge(m, sts)) # activate ST mode
- comb += dcbz_active.s.eq(rising_edge(m, dcbzs)) # activate DCBZ mode
# LD/ST requested activates "busy" (only if not already busy)
with m.If(self.pi.is_ld_i | self.pi.is_st_i):
- comb += busy_l.s.eq(~busy_delay)
+ with m.If(self.pi.exc_o.happened):
+ comb += busy_l.s.eq(0)
+ sync += Display("fast exception")
+ with m.Else():
+ comb += busy_l.s.eq(~busy_delay)
# if now in "LD" mode: wait for addr_ok, then send the address out
# to memory, acknowledge address, and send out LD data
comb += pi.addr_ok_o.eq(1) # acknowledge addr ok
sync += adrok_l.s.eq(1) # and pull "ack" latch
- # if now in "DCBZ" mode: wait for addr_ok, then send the address out
- # to memory, acknowledge address, and send out LD data
- with m.If(dcbz_active.q):
- ##comb += Display("dcbz active")
- # XXX Please don't do it this way, not without discussion
- # the exact same address is required to be set by both
- # dcbz and stores, so use the exact same function.
- # it would be better to add an extra argument to
- # set_wr_addr to indicate "dcbz mode".
- self.___use_wr_addr_instead_set_dcbz_addr(m, pi.addr.data)
-
# if now in "ST" mode: likewise do the same but with "ST"
# to memory, acknowledge address, and send out LD data
with m.If(st_active.q):
comb += lenexp.len_i.eq(pi.data_len)
comb += lenexp.addr_i.eq(lsbaddr)
with m.If(pi.addr.ok):
- self.set_wr_addr(m, pi.addr.data, lenexp.lexp_o, misalign, pr)
- with m.If(adrok_l.qn):
+ self.set_wr_addr(m, pi.addr.data, lenexp.lexp_o, misalign, pr,
+ pi.is_dcbz_i)
+ with m.If(adrok_l.qn & self.pi.exc_o.happened==0):
comb += pi.addr_ok_o.eq(1) # acknowledge addr ok
sync += adrok_l.s.eq(1) # and pull "ack" latch
with m.If(reset_l.q):
comb += ld_active.r.eq(1) # leave the LD active for 1 cycle
comb += st_active.r.eq(1) # leave the ST active for 1 cycle
- comb += dcbz_active.r.eq(1) # leave the DCBZ active for 1 cycle
comb += reset_l.r.eq(1) # clear reset
comb += adrok_l.r.eq(1) # address reset
comb += st_done.r.eq(1) # store done reset
# monitor for an exception, clear busy immediately
with m.If(self.pi.exc_o.happened):
comb += busy_l.r.eq(1)
+ comb += reset_l.s.eq(1) # also reset whole unit
# however ST needs one cycle before busy is reset
#with m.If(self.pi.st.ok | self.pi.ld.ok):
# hard-code memory addressing width to 6 bits
self.mem = TestMemory(regwid, 5, granularity=regwid//8, init=False)
- def set_wr_addr(self, m, addr, mask, misalign, msr_pr):
+ def set_wr_addr(self, m, addr, mask, misalign, msr_pr, is_dcbz):
lsbaddr, msbaddr = self.splitaddr(addr)
m.d.comb += self.mem.wrport.addr.eq(msbaddr)
projects / soc.git / blobdiff