stack of changes to MultiCompUnit to speed it up

[soc.git] / src / soc / experiment / pimem.py

diff --git a/src/soc/experiment/pimem.py b/src/soc/experiment/pimem.py
index 5e4351b8465ec6e51305211d5ce951baeaf8cf84..bc1daee125871b18c5280863a440e1cf73c44e0e 100644 (file)
--- a/src/soc/experiment/pimem.py
+++ b/src/soc/experiment/pimem.py
@@ -235,7 +235,11 @@ class PortInterfaceBase(Elaboratable):
 
         # LD/ST requested activates "busy" (only if not already busy)
         with m.If(self.pi.is_ld_i | self.pi.is_st_i):
-            comb += busy_l.s.eq(~busy_delay)
+            with m.If(self.pi.exc_o.happened):
+                comb += busy_l.s.eq(0)
+                sync += Display("fast exception")
+            with m.Else():
+                comb += busy_l.s.eq(~busy_delay)
 
         # if now in "LD" mode: wait for addr_ok, then send the address out
         # to memory, acknowledge address, and send out LD data
@@ -259,7 +263,7 @@ class PortInterfaceBase(Elaboratable):
             with m.If(pi.addr.ok):
                 self.set_wr_addr(m, pi.addr.data, lenexp.lexp_o, misalign, pr,
                                  pi.is_dcbz_i)
-                with m.If(adrok_l.qn):
+                with m.If(adrok_l.qn & self.pi.exc_o.happened==0):
                     comb += pi.addr_ok_o.eq(1)  # acknowledge addr ok
                     sync += adrok_l.s.eq(1)       # and pull "ack" latch
 
@@ -308,6 +312,7 @@ class PortInterfaceBase(Elaboratable):
         # monitor for an exception, clear busy immediately
         with m.If(self.pi.exc_o.happened):
             comb += busy_l.r.eq(1)
+            comb += reset_l.s.eq(1) # also reset whole unit
 
         # however ST needs one cycle before busy is reset
         #with m.If(self.pi.st.ok | self.pi.ld.ok):