add bare wishbone option to TestIssuer, sort out ports

[soc.git] / src / soc / experiment / pimem.py

diff --git a/src/soc/experiment/pimem.py b/src/soc/experiment/pimem.py
index 102f1869f36e8a0e8629be6f315d0ce16ab477e7..cdc82e17ae20b0f3e6a41a6233604b861587bf35 100644 (file)
--- a/src/soc/experiment/pimem.py
+++ b/src/soc/experiment/pimem.py
@@ -271,8 +271,7 @@ class PortInterfaceBase(Elaboratable):
         return m
 
     def ports(self):
-        for p in self.dports:
-            yield from p.ports()
+        yield from self.pi.ports()
 
 
 class TestMemoryPortInterface(PortInterfaceBase):