from nmigen.utils import log2_int
from nmutil.latch import SRLatch, latchregister
+from nmutil.util import rising_edge
from soc.decoder.power_decoder2 import Data
from soc.scoreboard.addr_match import LenExpand
+from soc.experiment.mem_types import LDSTException
# for testing purposes
from soc.experiment.testmem import TestMemory
+#from soc.scoreboard.addr_split import LDSTSplitter
import unittest
for the L0 Cache/Buffer to have an additional address latch
(because the LDSTCompUnit already has it)
- * addr_ok_o (or addr_exc_o) must be waited for. these will
+ * addr_ok_o (or exception.happened) must be waited for. these will
be asserted *only* for one cycle and one cycle only.
- * addr_exc_o will be asserted if there is no chance that the
+ * exception.happened will be asserted if there is no chance that the
memory request may be fulfilled.
- busy_o is deasserted on the same cycle as addr_exc_o is asserted.
+ busy_o is deasserted on the same cycle as exception.happened is asserted.
* conversely: addr_ok_o must *ONLY* be asserted if there is a
HUNDRED PERCENT guarantee that the memory request will be
self.addr = Data(addrwid, "addr_i") # addr/addr-ok
# addr is valid (TLB, L1 etc.)
self.addr_ok_o = Signal(reset_less=True)
- self.addr_exc_o = Signal(reset_less=True) # TODO, "type" of exception
+ self.exception_o = LDSTException("exc")
# LD/ST
self.ld = Data(regwid, "ld_data_o") # ok to be set by L0 Cache/Buf
self.st = Data(regwid, "st_data_i") # ok to be set by CompUnit
+ # additional "modes"
+ self.dcbz = Signal() # data cache block zero request
+ self.nc = Signal() # no cacheing
+ self.virt_mode = Signal() # virtual mode
+ self.priv_mode = Signal() # privileged mode
+
+ # mmu
+ self.mmu_done = Signal() # keep for now
+
+ # dcache
+ self.ldst_error = Signal()
+ ## Signalling ld/st error - NC cache hit, TLB miss, prot/RC failure
+ self.cache_paradox = Signal()
+
def connect_port(self, inport):
- print ("connect_port", self, inport)
+ print("connect_port", self, inport)
return [self.is_ld_i.eq(inport.is_ld_i),
self.is_st_i.eq(inport.is_st_i),
self.data_len.eq(inport.data_len),
inport.ld.eq(self.ld),
inport.busy_o.eq(self.busy_o),
inport.addr_ok_o.eq(self.addr_ok_o),
- inport.addr_exc_o.eq(self.addr_exc_o),
+ inport.exception_o.eq(self.exception_o),
+ inport.mmu_done.eq(self.mmu_done),
+ inport.ldst_error.eq(self.ldst_error),
+ inport.cache_paradox.eq(self.cache_paradox)
]
@property
def addrbits(self):
- return log2_int(self.mem.regwid//8)
+ return log2_int(self.regwid//8)
def splitaddr(self, addr):
"""split the address into top and bottom bits of the memory granularity
def connect_port(self, inport):
return self.pi.connect_port(inport)
- def set_wr_addr(self, m, addr): pass
- def set_rd_addr(self, m, addr): pass
+ def set_wr_addr(self, m, addr, mask): pass
+ def set_rd_addr(self, m, addr, mask): pass
def set_wr_data(self, m, data, wen): pass
def get_rd_data(self, m): pass
# state-machine latches
m.submodules.st_active = st_active = SRLatch(False, name="st_active")
+ m.submodules.st_done = st_done = SRLatch(False, name="st_done")
m.submodules.ld_active = ld_active = SRLatch(False, name="ld_active")
m.submodules.reset_l = reset_l = SRLatch(True, name="reset")
m.submodules.adrok_l = adrok_l = SRLatch(False, name="addr_acked")
m.submodules.busy_l = busy_l = SRLatch(False, name="busy")
m.submodules.cyc_l = cyc_l = SRLatch(True, name="cyc")
+
+ self.busy_l = busy_l
+
+ sync += st_done.s.eq(0)
+ comb += st_done.r.eq(0)
+ comb += st_active.r.eq(0)
+ comb += ld_active.r.eq(0)
comb += cyc_l.s.eq(0)
comb += cyc_l.r.eq(0)
+ comb += busy_l.s.eq(0)
+ comb += busy_l.r.eq(0)
sync += adrok_l.s.eq(0)
comb += adrok_l.r.eq(0)
lds = Signal(reset_less=True)
sts = Signal(reset_less=True)
pi = self.pi
- comb += lds.eq(pi.is_ld_i & pi.busy_o) # ld-req signals
- comb += sts.eq(pi.is_st_i & pi.busy_o) # st-req signals
+ comb += lds.eq(pi.is_ld_i) # ld-req signals
+ comb += sts.eq(pi.is_st_i) # st-req signals
+
+ # detect busy "edge"
+ busy_delay = Signal()
+ busy_edge = Signal()
+ sync += busy_delay.eq(pi.busy_o)
+ comb += busy_edge.eq(pi.busy_o & ~busy_delay)
- # activate mode
- with m.If(lds):
- comb += ld_active.s.eq(1) # activate LD mode
- with m.Elif(sts):
- comb += st_active.s.eq(1) # activate ST mode
+ # activate mode: only on "edge"
+ comb += ld_active.s.eq(rising_edge(m, lds)) # activate LD mode
+ comb += st_active.s.eq(rising_edge(m, sts)) # activate ST mode
+
+ # LD/ST requested activates "busy" (only if not already busy)
+ with m.If(self.pi.is_ld_i | self.pi.is_st_i):
+ comb += busy_l.s.eq(~busy_delay)
# if now in "LD" mode: wait for addr_ok, then send the address out
# to memory, acknowledge address, and send out LD data
comb += lenexp.len_i.eq(pi.data_len)
comb += lenexp.addr_i.eq(lsbaddr)
with m.If(pi.addr.ok & adrok_l.qn):
- self.set_rd_addr(m, msbaddr) # addr ok, send thru
+ self.set_rd_addr(m, pi.addr.data, lenexp.lexp_o)
comb += pi.addr_ok_o.eq(1) # acknowledge addr ok
sync += adrok_l.s.eq(1) # and pull "ack" latch
comb += lenexp.len_i.eq(pi.data_len)
comb += lenexp.addr_i.eq(lsbaddr)
with m.If(pi.addr.ok):
- self.set_wr_addr(m, msbaddr) # addr ok, send thru
+ self.set_wr_addr(m, pi.addr.data, lenexp.lexp_o)
with m.If(adrok_l.qn):
comb += pi.addr_ok_o.eq(1) # acknowledge addr ok
sync += adrok_l.s.eq(1) # and pull "ack" latch
# is a "Memory" test-class) the memory read data is valid.
comb += reset_l.s.eq(0)
comb += reset_l.r.eq(0)
+ lddata = Signal(self.regwid, reset_less=True)
+ data, ldok = self.get_rd_data(m)
+ comb += lddata.eq((data & lenexp.rexp_o) >>
+ (lenexp.addr_i*8))
with m.If(ld_active.q & adrok_l.q):
# shift data down before pushing out. requires masking
# from the *byte*-expanded version of LenExpand output
- lddata = Signal(self.regwid, reset_less=True)
- data, ldok = self.get_rd_data(m)
- comb += lddata.eq((data & lenexp.rexp_o) >>
- (lenexp.addr_i*8))
comb += pi.ld.data.eq(lddata) # put data out
comb += pi.ld.ok.eq(ldok) # indicate data valid
comb += reset_l.s.eq(ldok) # reset mode after 1 cycle
# TODO: replace with link to LoadStoreUnitInterface.x_store_data
# and also handle the ready/stall/busy protocol
stok = self.set_wr_data(m, stdata, lenexp.lexp_o)
+ sync += st_done.s.eq(1) # store done trigger
+ with m.If(st_done.q):
comb += reset_l.s.eq(stok) # reset mode after 1 cycle
# ugly hack, due to simultaneous addr req-go acknowledge
comb += st_active.r.eq(1) # leave the ST active for 1 cycle
comb += reset_l.r.eq(1) # clear reset
comb += adrok_l.r.eq(1) # address reset
-
- # LD/ST requested activates "busy"
- with m.If(self.pi.is_ld_i | self.pi.is_st_i):
- comb += busy_l.s.eq(1)
+ comb += st_done.r.eq(1) # store done reset
# monitor for an exception or the completion of LD.
- with m.If(self.pi.addr_exc_o):
+ with m.If(self.pi.exception_o.happened):
comb += busy_l.r.eq(1)
# however ST needs one cycle before busy is reset
- with m.If(self.pi.st.ok | self.pi.ld.ok):
+ #with m.If(self.pi.st.ok | self.pi.ld.ok):
+ with m.If(reset_l.s):
comb += cyc_l.s.eq(1)
with m.If(cyc_l.q):
comb += busy_l.r.eq(1)
# busy latch outputs to interface
- comb += self.pi.busy_o.eq(busy_l.q)
+ comb += pi.busy_o.eq(busy_l.q)
return m
def ports(self):
- for p in self.dports:
- yield from p.ports()
+ yield from self.pi.ports()
class TestMemoryPortInterface(PortInterfaceBase):
# hard-code memory addressing width to 6 bits
self.mem = TestMemory(regwid, 5, granularity=regwid//8, init=False)
- def set_wr_addr(self, m, addr):
- m.d.comb += self.mem.wrport.addr.eq(addr)
+ def set_wr_addr(self, m, addr, mask):
+ lsbaddr, msbaddr = self.splitaddr(addr)
+ m.d.comb += self.mem.wrport.addr.eq(msbaddr)
- def set_rd_addr(self, m, addr):
- m.d.comb += self.mem.rdport.addr.eq(addr)
+ def set_rd_addr(self, m, addr, mask):
+ lsbaddr, msbaddr = self.splitaddr(addr)
+ m.d.comb += self.mem.rdport.addr.eq(msbaddr)
def set_wr_data(self, m, data, wen):
m.d.comb += self.mem.wrport.data.eq(data) # write st to mem
- m.d.comb += self.mem.wrport.en.eq(wen) # enable writes
+ m.d.comb += self.mem.wrport.en.eq(wen) # enable writes
return Const(1, 1)
def get_rd_data(self, m):
def ports(self):
yield from super().ports()
# TODO: memory ports
-
-
projects / soc.git / blobdiff