from nmigen.cli import verilog, rtlil
from nmigen.hdl.ast import unsigned
from nmigen import Module, Const, Signal, Array, Cat, Elaboratable, Memory
+from nmigen.back.pysim import Delay
from soc.regfile.regfile import RegFileArray, treereduce
from soc.scoreboard.fu_fu_matrix import FUFUDepMatrix
from soc.experiment.compldst import LDSTCompUnit
from soc.experiment.testmem import TestMemory
-from soc.experiment.alu_hier import ALU, BranchALU
+from soc.experiment.alu_hier import ALU, BranchALU, CompALUOpSubset
+
+from soc.decoder.power_enums import MicrOp, Function
+from soc.decoder.power_decoder import (create_pdecode)
+from soc.decoder.power_decoder2 import (PowerDecode2)
+from soc.simulator.program import Program
+
+
from nmutil.latch import SRLatch
from nmutil.nmoperator import eq
self.opwid = opwid
# inputs
+ self.op = CompALUOpSubset("cua_i")
self.oper_i = Signal(opwid, reset_less=True)
self.imm_i = Signal(rwid, reset_less=True)
units = []
for alu in alus:
aluopwid = 3 # extra bit for immediate mode
- units.append(ComputationUnitNoDelay(rwid, aluopwid, alu))
+ units.append(ComputationUnitNoDelay(rwid, alu))
CompUnitsBase.__init__(self, rwid, units)
m = CompUnitsBase.elaborate(self, platform)
comb = m.d.comb
- # hand the same operation to all units, only lower 3 bits though
+ # hand the subset of operation to ALUs
for alu in self.units:
- comb += alu.oper_i[0:3].eq(self.oper_i)
- comb += alu.imm_i.eq(self.imm_i)
+ comb += alu.oper_i.eq(self.op)
+ #comb += alu.oper_i[0:3].eq(self.oper_i)
+ #comb += alu.imm_i.eq(self.imm_i)
return m
# Branch ALU and CU
self.bgt = BranchALU(rwid)
aluopwid = 3 # extra bit for immediate mode
- self.br1 = ComputationUnitNoDelay(rwid, aluopwid, self.bgt)
+ self.br1 = ComputationUnitNoDelay(rwid, self.bgt)
CompUnitsBase.__init__(self, rwid, [self.br1])
def elaborate(self, platform):
# hand the same operation to all units
for alu in self.units:
comb += alu.oper_i.eq(self.oper_i)
- comb += alu.imm_i.eq(self.imm_i)
+ #comb += alu.imm_i.eq(self.imm_i)
return m
self.lsissue = IssueUnitGroup(2)
self.brissue = IssueUnitGroup(1)
# and these
- self.alu_oper_i = Signal(4, reset_less=True)
- self.alu_imm_i = Signal(rwid, reset_less=True)
+ self.alu_op = CompALUOpSubset("alu")
self.br_oper_i = Signal(4, reset_less=True)
self.br_imm_i = Signal(rwid, reset_less=True)
self.ls_oper_i = Signal(4, reset_less=True)
]
# take these to outside (issue needs them)
- comb += cua.oper_i.eq(self.alu_oper_i)
- comb += cua.imm_i.eq(self.alu_imm_i)
+ comb += cua.op.eq(self.alu_op)
comb += cub.oper_i.eq(self.br_oper_i)
comb += cub.imm_i.eq(self.br_imm_i)
comb += cul.oper_i.eq(self.ls_oper_i)
comb += int_src1.ren.eq(intfus.src1_rsel_o)
comb += int_src2.ren.eq(intfus.src2_rsel_o)
- # connect ALUs to regfule
+ # connect ALUs to regfile
comb += int_dest.data_i.eq(cu.data_o)
comb += cu.src1_i.eq(int_src1.data_o)
comb += cu.src2_i.eq(int_src2.data_o)
mqbits = unsigned(int(log(qlen) / log(2))+2)
self.p_add_i = Signal(mqbits) # instructions to add (from data_i)
self.p_ready_o = Signal() # instructions were added
- self.data_i = Instruction.nq(n_in, "data_i", rwid, opwid)
+ self.data_i = Instruction._nq(n_in, "data_i")
self.busy_o = Signal(reset_less=True) # at least one CU is busy
self.qlen_o = Signal(mqbits, reset_less=True)
# "resetting" done above (insn_i=0) could be re-ASSERTed.
with m.If(iq.qlen_o != 0):
# get the operands and operation
- imm = iq.data_o[0].imm_i
- dest = iq.data_o[0].dest_i
- src1 = iq.data_o[0].src1_i
- src2 = iq.data_o[0].src2_i
- op = iq.data_o[0].oper_i
- opi = iq.data_o[0].opim_i # immediate set
+ instr = iq.data_o[0]
+ imm = instr.imm_data.data
+ dest = instr.write_reg.data
+ src1 = instr.read_reg1.data
+ src2 = instr.read_reg2.data
+ op = instr.insn_type
+ fu = instr.fn_unit
+ opi = instr.imm_data.ok # immediate set
# set the src/dest regs
comb += sc.int_dest_i.eq(dest)
comb += sc.reg_enable_i.eq(1) # enable the regfile
# choose a Function-Unit-Group
- with m.If((op & (0x3 << 2)) != 0): # branch
+ with m.If(fu == Function.ALU): # alu
+ comb += sc.alu_op.eq_from_execute1(instr)
+ comb += sc.aluissue.insn_i.eq(1)
+ comb += wait_issue_alu.eq(1)
+ with m.Elif((op & (0x3 << 2)) != 0): # branch
comb += sc.br_oper_i.eq(Cat(op[0:2], opi))
comb += sc.br_imm_i.eq(imm)
comb += sc.brissue.insn_i.eq(1)
comb += sc.ls_imm_i.eq(imm)
comb += sc.lsissue.insn_i.eq(1)
comb += wait_issue_ls.eq(1)
- with m.Else(): # alu
- comb += sc.alu_oper_i.eq(Cat(op[0:2], opi))
- comb += sc.alu_imm_i.eq(imm)
- comb += sc.aluissue.insn_i.eq(1)
- comb += wait_issue_alu.eq(1)
# XXX TODO
# these indicate that the instruction is to be made
return list(self)
-def instr_q(dut, op, op_imm, imm, src1, src2, dest,
+def power_instr_q(dut, pdecode2, ins, code):
+ instrs = [pdecode2.e]
+
+ sendlen = 1
+ for idx, instr in enumerate(instrs):
+ yield dut.data_i[idx].eq(instr)
+ insn_type = yield instr.insn_type
+ fn_unit = yield instr.fn_unit
+ print("senddata ", idx, insn_type, fn_unit, instr)
+ yield dut.p_add_i.eq(sendlen)
+ yield
+ o_p_ready = yield dut.p_ready_o
+ while not o_p_ready:
+ yield
+ o_p_ready = yield dut.p_ready_o
+
+ yield dut.p_add_i.eq(0)
+
+
+def instr_q(dut, op, funit, op_imm, imm, src1, src2, dest,
branch_success, branch_fail):
- instrs = [{'oper_i': op, 'dest_i': dest, 'imm_i': imm, 'opim_i': op_imm,
- 'src1_i': src1, 'src2_i': src2}]
+ instrs = [{'insn_type': op, 'fn_unit': funit, 'write_reg': dest,
+ 'imm_data': (imm, op_imm),
+ 'read_reg1': src1, 'read_reg2': src2}]
sendlen = 1
- for idx in range(sendlen):
- yield from eq(dut.data_i[idx], instrs[idx])
+ for idx, instr in enumerate(instrs):
+ imm, op_imm = instr['imm_data']
+ reg1 = instr['read_reg1']
+ reg2 = instr['read_reg2']
+ dest = instr['write_reg']
+ insn_type = instr['insn_type']
+ fn_unit = instr['fn_unit']
+ yield dut.data_i[idx].insn_type.eq(insn_type)
+ yield dut.data_i[idx].fn_unit.eq(fn_unit)
+ yield dut.data_i[idx].read_reg1.data.eq(reg1)
+ yield dut.data_i[idx].read_reg1.ok.eq(1) # XXX TODO
+ yield dut.data_i[idx].read_reg2.data.eq(reg2)
+ yield dut.data_i[idx].read_reg2.ok.eq(1) # XXX TODO
+ yield dut.data_i[idx].write_reg.data.eq(dest)
+ yield dut.data_i[idx].write_reg.ok.eq(1) # XXX TODO
+ yield dut.data_i[idx].imm_data.data.eq(imm)
+ yield dut.data_i[idx].imm_data.ok.eq(op_imm)
di = yield dut.data_i[idx]
print("senddata %d %x" % (idx, di))
yield dut.p_add_i.eq(sendlen)
yield from alusim.dump(dut)
+def power_sim(m, dut, pdecode2, instruction, alusim):
+
+ seed(0)
+
+ for i in range(1):
+
+ # set random values in the registers
+ for i in range(1, dut.n_regs):
+ #val = randint(0, (1<<alusim.rwidth)-1)
+ #val = 31+i*3
+ val = i # XXX actually, not random at all
+ yield dut.intregs.regs[i].reg.eq(val)
+ alusim.setval(i, val)
+
+ # create some instructions
+ lst = ["addi 3, 0, 0x1234",
+ "addi 2, 0, 0x4321",
+ "add 1, 3, 2"]
+ with Program(lst) as program:
+ gen = program.generate_instructions()
+
+ # issue instruction(s), wait for issue to be free before proceeding
+ for ins, code in zip(gen, program.assembly.splitlines()):
+ yield instruction.eq(ins) # raw binary instr.
+ yield Delay(1e-6)
+
+ print("binary 0x{:X}".format(ins & 0xffffffff))
+ print("assembly", code)
+
+ #alusim.op(op, opi, imm, src1, src2, dest)
+ yield from power_instr_q(dut, pdecode2, ins, code)
+
+ # wait for all instructions to stop before checking
+ while True:
+ iqlen = yield dut.qlen_o
+ if iqlen == 0:
+ break
+ yield
+ yield
+ yield
+ yield
+ yield
+ yield from wait_for_busy_clear(dut)
+
+ # check status
+ yield from alusim.check(dut)
+ yield from alusim.dump(dut)
+
+
def scoreboard_sim(dut, alusim):
seed(0)
if False:
instrs = create_random_ops(dut, 15, True, 4)
- if True: # LD/ST test (with immediate)
+ if False: # LD/ST test (with immediate)
instrs.append((1, 2, 0, 0x20, 1, 1, (0, 0))) # LD
#instrs.append( (1, 2, 0, 0x10, 1, 1, (0, 0)) )
- if True:
+ if False:
instrs.append((1, 2, 2, 1, 1, 20, (0, 0)))
- if True:
+ if False:
instrs.append((7, 3, 2, 4, 0, 0, (0, 0)))
instrs.append((7, 6, 6, 2, 0, 0, (0, 0)))
instrs.append((1, 7, 2, 2, 0, 0, (0, 0)))
if True:
+ instrs.append((2, 3, 3, MicrOp.OP_ADD, Function.ALU,
+ 0, 0, (0, 0)))
+ instrs.append((5, 3, 3, MicrOp.OP_ADD, Function.ALU,
+ 0, 0, (0, 0)))
+ if False:
+ instrs.append((3, 5, 5, MicrOp.OP_MUL_L64, Function.ALU,
+ 1, 7, (0, 0)))
+ if False:
+ instrs.append((2, 3, 3, MicrOp.OP_ADD, Function.ALU,
+ 0, 0, (0, 0)))
+
+ if False:
instrs.append((2, 3, 3, 0, 0, 0, (0, 0)))
instrs.append((5, 3, 3, 1, 0, 0, (0, 0)))
instrs.append((3, 5, 5, 2, 0, 0, (0, 0)))
# issue instruction(s), wait for issue to be free before proceeding
for i, instr in enumerate(instrs):
- src1, src2, dest, op, opi, imm, (br_ok, br_fail) = instr
+ print(i, instr)
+ src1, src2, dest, op, fn_unit, opi, imm, (br_ok, br_fail) = instr
- print("instr %d: (%d, %d, %d, %d, %d, %d)" %
- (i, src1, src2, dest, op, opi, imm))
+ print("instr %d: (%d, %d, %d, %s, %s, %d, %d)" %
+ (i, src1, src2, dest, op, fn_unit, opi, imm))
alusim.op(op, opi, imm, src1, src2, dest)
- yield from instr_q(dut, op, opi, imm, src1, src2, dest,
+ yield from instr_q(dut, op, fn_unit, opi, imm, src1, src2, dest,
br_ok, br_fail)
# wait for all instructions to stop before checking
def test_scoreboard():
- dut = IssueToScoreboard(2, 1, 1, 16, 8, 8)
- alusim = RegSim(16, 8)
+ regwidth = 64
+ dut = IssueToScoreboard(2, 1, 1, regwidth, 8, 8)
+ alusim = RegSim(regwidth, 8)
memsim = MemSim(16, 8)
- vl = rtlil.convert(dut, ports=dut.ports())
+
+ m = Module()
+ comb = m.d.comb
+ instruction = Signal(32)
+
+ # set up the decoder (and simulator, later)
+ pdecode = create_pdecode()
+ #simulator = ISA(pdecode, initial_regs)
+
+ m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
+ m.submodules.sim = dut
+
+ comb += pdecode2.dec.raw_opcode_in.eq(instruction)
+ comb += pdecode2.dec.bigendian.eq(0) # little / big?
+
+ vl = rtlil.convert(m, ports=dut.ports())
with open("test_scoreboard6600.il", "w") as f:
f.write(vl)
- run_simulation(dut, scoreboard_sim(dut, alusim),
- vcd_name='test_scoreboard6600.vcd')
+ run_simulation(m, power_sim(m, dut, pdecode2, instruction, alusim),
+ vcd_name='test_powerboard6600.vcd')
+
+ # run_simulation(dut, scoreboard_sim(dut, alusim),
+ # vcd_name='test_scoreboard6600.vcd')
# run_simulation(dut, scoreboard_branch_sim(dut, alusim),
# vcd_name='test_scoreboard6600.vcd')
projects / soc.git / blobdiff