from nmigen.cli import verilog, rtlil
from nmigen.hdl.ast import unsigned
from nmigen import Module, Const, Signal, Array, Cat, Elaboratable, Memory
+from nmigen.back.pysim import Delay
from soc.regfile.regfile import RegFileArray, treereduce
from soc.scoreboard.fu_fu_matrix import FUFUDepMatrix
from soc.experiment.alu_hier import ALU, BranchALU, CompALUOpSubset
-from soc.decoder.power_enums import InternalOp, Function
+from soc.decoder.power_enums import MicrOp, Function
+from soc.decoder.power_decoder import (create_pdecode)
+from soc.decoder.power_decoder2 import (PowerDecode2)
+from soc.simulator.program import Program
+
from nmutil.latch import SRLatch
from nmutil.nmoperator import eq
# hand the same operation to all units
for alu in self.units:
comb += alu.oper_i.eq(self.oper_i)
- comb += alu.imm_i.eq(self.imm_i)
+ #comb += alu.imm_i.eq(self.imm_i)
return m
comb += int_src1.ren.eq(intfus.src1_rsel_o)
comb += int_src2.ren.eq(intfus.src2_rsel_o)
- # connect ALUs to regfule
+ # connect ALUs to regfile
comb += int_dest.data_i.eq(cu.data_o)
comb += cu.src1_i.eq(int_src1.data_o)
comb += cu.src2_i.eq(int_src2.data_o)
return list(self)
+def power_instr_q(dut, pdecode2, ins, code):
+ instrs = [pdecode2.e]
+
+ sendlen = 1
+ for idx, instr in enumerate(instrs):
+ yield dut.data_i[idx].eq(instr)
+ insn_type = yield instr.insn_type
+ fn_unit = yield instr.fn_unit
+ print("senddata ", idx, insn_type, fn_unit, instr)
+ yield dut.p_add_i.eq(sendlen)
+ yield
+ o_p_ready = yield dut.p_ready_o
+ while not o_p_ready:
+ yield
+ o_p_ready = yield dut.p_ready_o
+
+ yield dut.p_add_i.eq(0)
+
+
def instr_q(dut, op, funit, op_imm, imm, src1, src2, dest,
branch_success, branch_fail):
instrs = [{'insn_type': op, 'fn_unit': funit, 'write_reg': dest,
- 'imm_data': (imm, op_imm),
+ 'imm_data': (imm, op_imm),
'read_reg1': src1, 'read_reg2': src2}]
sendlen = 1
yield dut.data_i[idx].insn_type.eq(insn_type)
yield dut.data_i[idx].fn_unit.eq(fn_unit)
yield dut.data_i[idx].read_reg1.data.eq(reg1)
- yield dut.data_i[idx].read_reg1.ok.eq(1) # XXX TODO
+ yield dut.data_i[idx].read_reg1.ok.eq(1) # XXX TODO
yield dut.data_i[idx].read_reg2.data.eq(reg2)
- yield dut.data_i[idx].read_reg2.ok.eq(1) # XXX TODO
+ yield dut.data_i[idx].read_reg2.ok.eq(1) # XXX TODO
yield dut.data_i[idx].write_reg.data.eq(dest)
- yield dut.data_i[idx].write_reg.ok.eq(1) # XXX TODO
+ yield dut.data_i[idx].write_reg.ok.eq(1) # XXX TODO
yield dut.data_i[idx].imm_data.data.eq(imm)
yield dut.data_i[idx].imm_data.ok.eq(op_imm)
di = yield dut.data_i[idx]
yield from alusim.dump(dut)
+def power_sim(m, dut, pdecode2, instruction, alusim):
+
+ seed(0)
+
+ for i in range(1):
+
+ # set random values in the registers
+ for i in range(1, dut.n_regs):
+ #val = randint(0, (1<<alusim.rwidth)-1)
+ #val = 31+i*3
+ val = i # XXX actually, not random at all
+ yield dut.intregs.regs[i].reg.eq(val)
+ alusim.setval(i, val)
+
+ # create some instructions
+ lst = ["addi 3, 0, 0x1234",
+ "addi 2, 0, 0x4321",
+ "add 1, 3, 2"]
+ with Program(lst) as program:
+ gen = program.generate_instructions()
+
+ # issue instruction(s), wait for issue to be free before proceeding
+ for ins, code in zip(gen, program.assembly.splitlines()):
+ yield instruction.eq(ins) # raw binary instr.
+ yield Delay(1e-6)
+
+ print("binary 0x{:X}".format(ins & 0xffffffff))
+ print("assembly", code)
+
+ #alusim.op(op, opi, imm, src1, src2, dest)
+ yield from power_instr_q(dut, pdecode2, ins, code)
+
+ # wait for all instructions to stop before checking
+ while True:
+ iqlen = yield dut.qlen_o
+ if iqlen == 0:
+ break
+ yield
+ yield
+ yield
+ yield
+ yield
+ yield from wait_for_busy_clear(dut)
+
+ # check status
+ yield from alusim.check(dut)
+ yield from alusim.dump(dut)
+
+
def scoreboard_sim(dut, alusim):
seed(0)
instrs.append((7, 6, 6, 2, 0, 0, (0, 0)))
instrs.append((1, 7, 2, 2, 0, 0, (0, 0)))
- if False:
- instrs.append((2, 3, 3, InternalOp.OP_ADD, Function.ALU,
+ if True:
+ instrs.append((2, 3, 3, MicrOp.OP_ADD, Function.ALU,
0, 0, (0, 0)))
- instrs.append((5, 3, 3, InternalOp.OP_ADD, Function.ALU,
+ instrs.append((5, 3, 3, MicrOp.OP_ADD, Function.ALU,
0, 0, (0, 0)))
- if True:
- instrs.append((3, 5, 5, InternalOp.OP_MUL_L64, Function.ALU,
+ if False:
+ instrs.append((3, 5, 5, MicrOp.OP_MUL_L64, Function.ALU,
1, 7, (0, 0)))
if False:
- instrs.append((2, 3, 3, InternalOp.OP_ADD, Function.ALU,
+ instrs.append((2, 3, 3, MicrOp.OP_ADD, Function.ALU,
0, 0, (0, 0)))
if False:
# issue instruction(s), wait for issue to be free before proceeding
for i, instr in enumerate(instrs):
- print (i, instr)
+ print(i, instr)
src1, src2, dest, op, fn_unit, opi, imm, (br_ok, br_fail) = instr
print("instr %d: (%d, %d, %d, %s, %s, %d, %d)" %
dut = IssueToScoreboard(2, 1, 1, regwidth, 8, 8)
alusim = RegSim(regwidth, 8)
memsim = MemSim(16, 8)
- vl = rtlil.convert(dut, ports=dut.ports())
+
+ m = Module()
+ comb = m.d.comb
+ instruction = Signal(32)
+
+ # set up the decoder (and simulator, later)
+ pdecode = create_pdecode()
+ #simulator = ISA(pdecode, initial_regs)
+
+ m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
+ m.submodules.sim = dut
+
+ comb += pdecode2.dec.raw_opcode_in.eq(instruction)
+ comb += pdecode2.dec.bigendian.eq(0) # little / big?
+
+ vl = rtlil.convert(m, ports=dut.ports())
with open("test_scoreboard6600.il", "w") as f:
f.write(vl)
- run_simulation(dut, scoreboard_sim(dut, alusim),
- vcd_name='test_scoreboard6600.vcd')
+ run_simulation(m, power_sim(m, dut, pdecode2, instruction, alusim),
+ vcd_name='test_powerboard6600.vcd')
+
+ # run_simulation(dut, scoreboard_sim(dut, alusim),
+ # vcd_name='test_scoreboard6600.vcd')
# run_simulation(dut, scoreboard_branch_sim(dut, alusim),
# vcd_name='test_scoreboard6600.vcd')
projects / soc.git / blobdiff