Choose between RA (src1) and zero immediate, conditioned on zero_a

[soc.git] / src / soc / experiment / score6600_multi.py

diff --git a/src/soc/experiment/score6600_multi.py b/src/soc/experiment/score6600_multi.py
index 4159d99ecafc50fe36b033bedac7a1e48e540ae3..46398bd95c6833b3ecfff50580d716853de005e5 100644 (file)
--- a/src/soc/experiment/score6600_multi.py
+++ b/src/soc/experiment/score6600_multi.py
@@ -20,7 +20,8 @@ from soc.experiment.compldst_multi import LDSTCompUnit
 from soc.experiment.compldst_multi import CompLDSTOpSubset
 from soc.experiment.l0_cache import TstL0CacheBuffer
 
-from soc.experiment.alu_hier import ALU, BranchALU, CompALUOpSubset
+from soc.experiment.alu_hier import ALU, BranchALU
+from soc.fu.alu.alu_input_record import CompALUOpSubset
 
 from soc.decoder.power_enums import InternalOp, Function
 from soc.decoder.power_decoder import (create_pdecode)
@@ -264,7 +265,7 @@ class CompUnitALUs(CompUnitsBase):
         units = []
         for alu in alus:
             aluopwid = 3  # extra bit for immediate mode
-            units.append(MultiCompUnit(rwid, alu))
+            units.append(MultiCompUnit(rwid, alu, CompALUOpSubset))
 
         CompUnitsBase.__init__(self, rwid, units)
 
@@ -300,7 +301,7 @@ class CompUnitBR(CompUnitsBase):
         # Branch ALU and CU
         self.bgt = BranchALU(rwid)
         aluopwid = 3  # extra bit for immediate mode
-        self.br1 = MultiCompUnit(rwid, self.bgt)
+        self.br1 = MultiCompUnit(rwid, self.bgt, CompALUOpSubset)
         CompUnitsBase.__init__(self, rwid, [self.br1])
 
     def elaborate(self, platform):
@@ -1161,7 +1162,8 @@ def power_sim(m, dut, pdecode2, instruction, alusim):
                    "add  4, 3, 5"
                     ]
         if True:
-            lst += [ "lbz 6, 7(2)",
+            lst += [ "lbzu 6, 7(2)",
+                     
                    ]
 
         with Program(lst) as program: