eek, first cut at using POWER decoder2 in 6600 simulator, barely working

[soc.git] / src / soc / experiment / sim.py

diff --git a/src/soc/experiment/sim.py b/src/soc/experiment/sim.py
index d24b013ddb63355863d24c27b1e5f48cdead56b4..531e95343a2054a6567c4406133464b7f5bc3f3b 100644 (file)
--- a/src/soc/experiment/sim.py
+++ b/src/soc/experiment/sim.py
@@ -42,7 +42,7 @@ class RegSim:
             src2 = imm
         else:
             src2 = self.regs[src2] & maxbits
-        if op == IADD:
+        if op == InternalOp.OP_ADD:
             val = src1 + src2
         elif op == ISUB:
             val = src1 - src2