remove zero/invert from ShiftRot Input Record

[soc.git] / src / soc / experiment / sim.py

diff --git a/src/soc/experiment/sim.py b/src/soc/experiment/sim.py
index 66b37ee878b424ebccb23029ca0afed1fe788a8a..1c725b25798a56e12967a04bbbff78a5b56d968d 100644 (file)
--- a/src/soc/experiment/sim.py
+++ b/src/soc/experiment/sim.py
@@ -36,6 +36,7 @@ class RegSim:
         self.regs = [0] * nregs
 
     def op(self, op, op_imm, imm, src1, src2, dest):
+        print ("regsim op src1, src2", op, op_imm, imm, src1, src2, dest)
         maxbits = (1 << self.rwidth) - 1
         src1 = self.regs[src1] & maxbits
         if op_imm:
@@ -46,6 +47,7 @@ class RegSim:
             val = src1 + src2
         elif op == InternalOp.OP_MUL_L64:
             val = src1 * src2
+            print ("mul src1, src2", src1, src2, val)
         elif op == ISUB:
             val = src1 - src2
         elif op == ISHF: