from soc.fu.cr.cr_input_record import CompCROpSubset
from soc.experiment.alu_hier import ALU, DummyALU
from soc.experiment.compalu_multi import MultiCompUnit
-from soc.decoder.power_enums import MicrOp
+from openpower.decoder.power_enums import MicrOp
from nmutil.gtkw import write_gtkw
from nmigen import Module, Signal
from nmigen.cli import rtlil
rc=1, rdmaskn=[0, 1],
src_delays=[2, 1], dest_delays=[0, 2])
# 5 - 5 = 0
- # 0 == 0 => CR = 0b000
+ # 0 == 0 => CR = 0b001
yield from op.issue([5, 2], MicrOp.OP_CMP, [0, 0b001],
imm=5, imm_ok=1, rc=1,
src_delays=[0, 1], dest_delays=[2, 1])