Documented at http://libre-soc.org/3d_gpu/architecture/compunit
"""
+from soc.experiment.alu_fsm import Shifter, CompFSMOpSubset
+from soc.fu.alu.alu_input_record import CompALUOpSubset
+from soc.experiment.alu_hier import ALU, DummyALU
+from soc.experiment.compalu_multi import MultiCompUnit
+from soc.decoder.power_enums import MicrOp
+from nmigen import Module
+from nmigen.cli import rtlil
cxxsim = False
if cxxsim:
from nmigen.sim.cxxsim import Simulator, Settle
else:
from nmigen.back.pysim import Simulator, Settle
-from nmigen.cli import rtlil
-from nmigen import Module
-
-from soc.decoder.power_enums import MicrOp
-
-from soc.experiment.compalu_multi import MultiCompUnit
-from soc.experiment.alu_hier import ALU, DummyALU
-from soc.fu.alu.alu_input_record import CompALUOpSubset
-from soc.experiment.alu_fsm import Shifter, CompFSMOpSubset
def wrap(process):
def wrapper():
def op_sim_fsm(dut, a, b, direction):
- print ("op_sim_fsm", a, b, direction)
+ print("op_sim_fsm", a, b, direction)
yield dut.issue_i.eq(0)
yield
yield dut.src_i[0].eq(a)
while True:
yield
rd_rel_o = yield dut.rd.rel
- print ("rd_rel", rd_rel_o)
+ print("rd_rel", rd_rel_o)
if rd_rel_o:
break
yield dut.rd.go.eq(0)
req_rel_o = yield dut.wr.rel
result = yield dut.data_o
- print ("req_rel", req_rel_o, result)
+ print("req_rel", req_rel_o, result)
while True:
req_rel_o = yield dut.wr.rel
result = yield dut.data_o
- print ("req_rel", req_rel_o, result)
+ print("req_rel", req_rel_o, result)
if req_rel_o:
break
yield
yield Settle()
result = yield dut.data_o
yield
- print ("result", result)
+ print("result", result)
yield dut.wr.go[0].eq(0)
yield
return result
while True:
yield
rd_rel_o = yield dut.rd.rel
- print ("rd_rel", rd_rel_o)
+ print("rd_rel", rd_rel_o)
if rd_rel_o:
break
yield dut.rd.go.eq(0)
+ else:
+ print("no go rd")
+
if len(dut.src_i) == 3:
yield dut.rd.go.eq(0b100)
while True:
yield
rd_rel_o = yield dut.rd.rel
- print ("rd_rel", rd_rel_o)
+ print("rd_rel", rd_rel_o)
if rd_rel_o:
break
yield dut.rd.go.eq(0)
+ else:
+ print("no 3rd rd")
req_rel_o = yield dut.wr.rel
result = yield dut.data_o
- print ("req_rel", req_rel_o, result)
+ print("req_rel", req_rel_o, result)
while True:
req_rel_o = yield dut.wr.rel
result = yield dut.data_o
- print ("req_rel", req_rel_o, result)
+ print("req_rel", req_rel_o, result)
if req_rel_o:
break
yield
yield Settle()
result = yield dut.data_o
yield
- print ("result", result)
+ print("result", result)
yield dut.wr.go[0].eq(0)
yield
return result
def scoreboard_sim_dummy(dut):
result = yield from op_sim(dut, 5, 2, MicrOp.OP_NOP, inv_a=0,
- imm=8, imm_ok=1)
+ imm=8, imm_ok=1)
assert result == 5, result
result = yield from op_sim(dut, 9, 2, MicrOp.OP_NOP, inv_a=0,
- imm=8, imm_ok=1)
+ imm=8, imm_ok=1)
assert result == 9, result
-
def scoreboard_sim(dut):
+ # zero (no) input operands test
+ result = yield from op_sim(dut, 5, 2, MicrOp.OP_ADD, zero_a=1,
+ imm=8, imm_ok=1)
+ assert result == 8
+
result = yield from op_sim(dut, 5, 2, MicrOp.OP_ADD, inv_a=0,
- imm=8, imm_ok=1)
+ imm=8, imm_ok=1)
assert result == 13
result = yield from op_sim(dut, 5, 2, MicrOp.OP_ADD)
result = yield from op_sim(dut, 5, 2, MicrOp.OP_ADD, inv_a=1)
assert result == 65532
- result = yield from op_sim(dut, 5, 2, MicrOp.OP_ADD, zero_a=1,
- imm=8, imm_ok=1)
- assert result == 8
-
result = yield from op_sim(dut, 5, 2, MicrOp.OP_ADD, zero_a=1)
assert result == 2
inspec = [('INT', 'a', '0:15'),
('INT', 'b', '0:15'),
- ]
- outspec = [('INT', 'o', '0:15'),
]
+ outspec = [('INT', 'o', '0:15'),
+ ]
regspec = (inspec, outspec)
('INT', 'b', '0:15'),
('INT', 'c', '0:15')]
outspec = [('INT', 'o', '0:15'),
- ]
+ ]
regspec = (inspec, outspec)
inspec = [('INT', 'a', '0:15'),
('INT', 'b', '0:15')]
outspec = [('INT', 'o', '0:15'),
- ]
+ ]
regspec = (inspec, outspec)
if __name__ == '__main__':
- test_compunit_fsm()
test_compunit()
+ test_compunit_fsm()
test_compunit_regspec1()
test_compunit_regspec3()