rename invert_a to invert_in because logical inverts RB

[soc.git] / src / soc / experiment / test / test_compalu_multi.py

diff --git a/src/soc/experiment/test/test_compalu_multi.py b/src/soc/experiment/test/test_compalu_multi.py
index 4054de4c8e9eeca45a89db276a85209f56575cc8..97eb635f2f2c59d6a722c898b2bd6a3ac49a26a2 100644 (file)
--- a/src/soc/experiment/test/test_compalu_multi.py
+++ b/src/soc/experiment/test/test_compalu_multi.py
@@ -42,31 +42,31 @@ def op_sim_fsm(dut, a, b, direction):
     yield dut.issue_i.eq(0)
     yield
 
-    yield dut.rd.go.eq(0b11)
+    yield dut.rd.go_i.eq(0b11)
     while True:
         yield
-        rd_rel_o = yield dut.rd.rel
+        rd_rel_o = yield dut.rd.rel_o
         print("rd_rel", rd_rel_o)
         if rd_rel_o:
             break
-    yield dut.rd.go.eq(0)
+    yield dut.rd.go_i.eq(0)
 
-    req_rel_o = yield dut.wr.rel
+    req_rel_o = yield dut.wr.rel_o
     result = yield dut.data_o
     print("req_rel", req_rel_o, result)
     while True:
-        req_rel_o = yield dut.wr.rel
+        req_rel_o = yield dut.wr.rel_o
         result = yield dut.data_o
         print("req_rel", req_rel_o, result)
         if req_rel_o:
             break
         yield
-    yield dut.wr.go[0].eq(1)
+    yield dut.wr.go_i[0].eq(1)
     yield Settle()
     result = yield dut.data_o
     yield
     print("result", result)
-    yield dut.wr.go[0].eq(0)
+    yield dut.wr.go_i[0].eq(0)
     yield
     return result
 
@@ -77,7 +77,7 @@ def op_sim(dut, a, b, op, inv_a=0, imm=0, imm_ok=0, zero_a=0):
     yield dut.src_i[0].eq(a)
     yield dut.src_i[1].eq(b)
     yield dut.oper_i.insn_type.eq(op)
-    yield dut.oper_i.invert_a.eq(inv_a)
+    yield dut.oper_i.invert_in.eq(inv_a)
     yield dut.oper_i.imm_data.imm.eq(imm)
     yield dut.oper_i.imm_data.imm_ok.eq(imm_ok)
     yield dut.oper_i.zero_a.eq(zero_a)
@@ -86,45 +86,45 @@ def op_sim(dut, a, b, op, inv_a=0, imm=0, imm_ok=0, zero_a=0):
     yield dut.issue_i.eq(0)
     yield
     if not imm_ok or not zero_a:
-        yield dut.rd.go.eq(0b11)
+        yield dut.rd.go_i.eq(0b11)
         while True:
             yield
-            rd_rel_o = yield dut.rd.rel
+            rd_rel_o = yield dut.rd.rel_o
             print("rd_rel", rd_rel_o)
             if rd_rel_o:
                 break
-        yield dut.rd.go.eq(0)
+        yield dut.rd.go_i.eq(0)
     else:
         print("no go rd")
 
     if len(dut.src_i) == 3:
-        yield dut.rd.go.eq(0b100)
+        yield dut.rd.go_i.eq(0b100)
         while True:
             yield
-            rd_rel_o = yield dut.rd.rel
+            rd_rel_o = yield dut.rd.rel_o
             print("rd_rel", rd_rel_o)
             if rd_rel_o:
                 break
-        yield dut.rd.go.eq(0)
+        yield dut.rd.go_i.eq(0)
     else:
         print("no 3rd rd")
 
-    req_rel_o = yield dut.wr.rel
+    req_rel_o = yield dut.wr.rel_o
     result = yield dut.data_o
     print("req_rel", req_rel_o, result)
     while True:
-        req_rel_o = yield dut.wr.rel
+        req_rel_o = yield dut.wr.rel_o
         result = yield dut.data_o
         print("req_rel", req_rel_o, result)
         if req_rel_o:
             break
         yield
-    yield dut.wr.go[0].eq(1)
+    yield dut.wr.go_i[0].eq(1)
     yield Settle()
     result = yield dut.data_o
     yield
     print("result", result)
-    yield dut.wr.go[0].eq(0)
+    yield dut.wr.go_i[0].eq(0)
     yield
     return result
 
@@ -285,7 +285,7 @@ class CompUnitParallelTest:
 
         # at the same time, present the operation
         yield self.dut.oper_i.insn_type.eq(self.op)
-        yield self.dut.oper_i.invert_a.eq(self.inv_a)
+        yield self.dut.oper_i.invert_in.eq(self.inv_a)
         yield self.dut.oper_i.imm_data.imm.eq(self.imm)
         yield self.dut.oper_i.imm_data.imm_ok.eq(self.imm_ok)
         yield self.dut.oper_i.zero_a.eq(self.zero_a)
@@ -310,7 +310,7 @@ class CompUnitParallelTest:
         # note: rdmaskn must be held, while busy_o is active
         # TODO: deactivate rdmaskn when the busy_o cycle ends
         yield self.dut.oper_i.insn_type.eq(0)
-        yield self.dut.oper_i.invert_a.eq(0)
+        yield self.dut.oper_i.invert_in.eq(0)
         yield self.dut.oper_i.imm_data.imm.eq(0)
         yield self.dut.oper_i.imm_data.imm_ok.eq(0)
         yield self.dut.oper_i.zero_a.eq(0)
@@ -346,7 +346,7 @@ class CompUnitParallelTest:
             if issue_i:
                 break
             # issue_i has not risen yet, so rd must keep low
-            rel = yield self.dut.rd.rel[rd_idx]
+            rel = yield self.dut.rd.rel_o[rd_idx]
             assert not rel
             yield
 
@@ -360,24 +360,24 @@ class CompUnitParallelTest:
             return
 
         # issue_i has risen. rel must rise on the next cycle
-        rel = yield self.dut.rd.rel[rd_idx]
+        rel = yield self.dut.rd.rel_o[rd_idx]
         assert not rel
 
         # stall for additional cycles. Check that rel doesn't fall on its own
         for n in range(self.RD_GO_DELAY[rd_idx]):
             yield
-            rel = yield self.dut.rd.rel[rd_idx]
+            rel = yield self.dut.rd.rel_o[rd_idx]
             assert rel
 
         # Before asserting "go", make sure "rel" has risen.
         # The use of Settle allows "go" to be set combinatorially,
         # rising on the same cycle as "rel".
         yield Settle()
-        rel = yield self.dut.rd.rel[rd_idx]
+        rel = yield self.dut.rd.rel_o[rd_idx]
         assert rel
 
         # assert go for one cycle, passing along the operand value
-        yield self.dut.rd.go[rd_idx].eq(1)
+        yield self.dut.rd.go_i[rd_idx].eq(1)
         yield self.dut.src_i[rd_idx].eq(self.operands[rd_idx])
         # check that the operand was sent to the alu
         # TODO: Properly check the alu protocol
@@ -387,17 +387,17 @@ class CompUnitParallelTest:
         yield
 
         # rel must keep high, since go was inactive in the last cycle
-        rel = yield self.dut.rd.rel[rd_idx]
+        rel = yield self.dut.rd.rel_o[rd_idx]
         assert rel
 
         # finish the go one-clock pulse
-        yield self.dut.rd.go[rd_idx].eq(0)
+        yield self.dut.rd.go_i[rd_idx].eq(0)
         yield self.dut.src_i[rd_idx].eq(0)
         yield
 
         # rel must have gone low in response to go being high
         # on the previous cycle
-        rel = yield self.dut.rd.rel[rd_idx]
+        rel = yield self.dut.rd.rel_o[rd_idx]
         assert not rel
 
         self.rd_complete[rd_idx] = True