Documented at http://libre-soc.org/3d_gpu/architecture/compunit
"""
-from nmigen.compat.sim import run_simulation, Settle
-from nmigen.cli import rtlil
+from soc.experiment.alu_fsm import Shifter, CompFSMOpSubset
+from soc.fu.alu.alu_input_record import CompALUOpSubset
+from soc.experiment.alu_hier import ALU, DummyALU
+from soc.experiment.compalu_multi import MultiCompUnit
+from soc.decoder.power_enums import MicrOp
from nmigen import Module
+from nmigen.cli import rtlil
+cxxsim = False
+if cxxsim:
+ from nmigen.sim.cxxsim import Simulator, Settle
+else:
+ from nmigen.back.pysim import Simulator, Settle
-from soc.decoder.power_enums import InternalOp
-from soc.experiment.compalu_multi import MultiCompUnit
-from soc.experiment.alu_hier import ALU, DummyALU
-from soc.fu.alu.alu_input_record import CompALUOpSubset
+def wrap(process):
+ def wrapper():
+ yield from process
+ return wrapper
+
+
+def op_sim_fsm(dut, a, b, direction):
+ print("op_sim_fsm", a, b, direction)
+ yield dut.issue_i.eq(0)
+ yield
+ yield dut.src_i[0].eq(a)
+ yield dut.src_i[1].eq(b)
+ yield dut.oper_i.sdir.eq(direction)
+ yield dut.issue_i.eq(1)
+ yield
+ yield dut.issue_i.eq(0)
+ yield
+
+ yield dut.rd.go_i.eq(0b11)
+ while True:
+ yield
+ rd_rel_o = yield dut.rd.rel_o
+ print("rd_rel", rd_rel_o)
+ if rd_rel_o:
+ break
+ yield dut.rd.go_i.eq(0)
+
+ req_rel_o = yield dut.wr.rel_o
+ result = yield dut.data_o
+ print("req_rel", req_rel_o, result)
+ while True:
+ req_rel_o = yield dut.wr.rel_o
+ result = yield dut.data_o
+ print("req_rel", req_rel_o, result)
+ if req_rel_o:
+ break
+ yield
+ yield dut.wr.go_i[0].eq(1)
+ yield Settle()
+ result = yield dut.data_o
+ yield
+ print("result", result)
+ yield dut.wr.go_i[0].eq(0)
+ yield
+ return result
def op_sim(dut, a, b, op, inv_a=0, imm=0, imm_ok=0, zero_a=0):
yield dut.src_i[0].eq(a)
yield dut.src_i[1].eq(b)
yield dut.oper_i.insn_type.eq(op)
- yield dut.oper_i.invert_a.eq(inv_a)
+ yield dut.oper_i.invert_in.eq(inv_a)
yield dut.oper_i.imm_data.imm.eq(imm)
yield dut.oper_i.imm_data.imm_ok.eq(imm_ok)
yield dut.oper_i.zero_a.eq(zero_a)
yield dut.issue_i.eq(0)
yield
if not imm_ok or not zero_a:
- yield dut.rd.go.eq(0b11)
+ yield dut.rd.go_i.eq(0b11)
while True:
yield
- rd_rel_o = yield dut.rd.rel
- print ("rd_rel", rd_rel_o)
+ rd_rel_o = yield dut.rd.rel_o
+ print("rd_rel", rd_rel_o)
if rd_rel_o:
break
- yield dut.rd.go.eq(0)
+ yield dut.rd.go_i.eq(0)
+ else:
+ print("no go rd")
+
if len(dut.src_i) == 3:
- yield dut.rd.go.eq(0b100)
+ yield dut.rd.go_i.eq(0b100)
while True:
yield
- rd_rel_o = yield dut.rd.rel
- print ("rd_rel", rd_rel_o)
+ rd_rel_o = yield dut.rd.rel_o
+ print("rd_rel", rd_rel_o)
if rd_rel_o:
break
- yield dut.rd.go.eq(0)
+ yield dut.rd.go_i.eq(0)
+ else:
+ print("no 3rd rd")
- req_rel_o = yield dut.wr.rel
+ req_rel_o = yield dut.wr.rel_o
result = yield dut.data_o
- print ("req_rel", req_rel_o, result)
+ print("req_rel", req_rel_o, result)
while True:
- req_rel_o = yield dut.wr.rel
+ req_rel_o = yield dut.wr.rel_o
result = yield dut.data_o
- print ("req_rel", req_rel_o, result)
+ print("req_rel", req_rel_o, result)
if req_rel_o:
break
yield
- yield dut.wr.go[0].eq(1)
+ yield dut.wr.go_i[0].eq(1)
yield Settle()
result = yield dut.data_o
yield
- print ("result", result)
- yield dut.wr.go[0].eq(0)
+ print("result", result)
+ yield dut.wr.go_i[0].eq(0)
yield
return result
+def scoreboard_sim_fsm(dut):
+ result = yield from op_sim_fsm(dut, 13, 2, 1)
+ assert result == 3, result
+
+ result = yield from op_sim_fsm(dut, 3, 4, 0)
+ assert result == 48, result
+
+ result = yield from op_sim_fsm(dut, 21, 0, 0)
+ assert result == 21, result
+
+
def scoreboard_sim_dummy(dut):
- result = yield from op_sim(dut, 5, 2, InternalOp.OP_NOP, inv_a=0,
- imm=8, imm_ok=1)
+ result = yield from op_sim(dut, 5, 2, MicrOp.OP_NOP, inv_a=0,
+ imm=8, imm_ok=1)
assert result == 5, result
- result = yield from op_sim(dut, 9, 2, InternalOp.OP_NOP, inv_a=0,
- imm=8, imm_ok=1)
+ result = yield from op_sim(dut, 9, 2, MicrOp.OP_NOP, inv_a=0,
+ imm=8, imm_ok=1)
assert result == 9, result
def scoreboard_sim(dut):
- result = yield from op_sim(dut, 5, 2, InternalOp.OP_ADD, inv_a=0,
- imm=8, imm_ok=1)
+ # zero (no) input operands test
+ result = yield from op_sim(dut, 5, 2, MicrOp.OP_ADD, zero_a=1,
+ imm=8, imm_ok=1)
+ assert result == 8
+
+ result = yield from op_sim(dut, 5, 2, MicrOp.OP_ADD, inv_a=0,
+ imm=8, imm_ok=1)
assert result == 13
- result = yield from op_sim(dut, 5, 2, InternalOp.OP_ADD)
+ result = yield from op_sim(dut, 5, 2, MicrOp.OP_ADD)
assert result == 7
- result = yield from op_sim(dut, 5, 2, InternalOp.OP_ADD, inv_a=1)
+ result = yield from op_sim(dut, 5, 2, MicrOp.OP_ADD, inv_a=1)
assert result == 65532
- result = yield from op_sim(dut, 5, 2, InternalOp.OP_ADD, zero_a=1,
- imm=8, imm_ok=1)
- assert result == 8
-
- result = yield from op_sim(dut, 5, 2, InternalOp.OP_ADD, zero_a=1)
+ result = yield from op_sim(dut, 5, 2, MicrOp.OP_ADD, zero_a=1)
assert result == 2
# test combinatorial zero-delay operation
# In the test ALU, any operation other than ADD, MUL or SHR
# is zero-delay, and do a subtraction.
- result = yield from op_sim(dut, 5, 2, InternalOp.OP_NOP)
+ result = yield from op_sim(dut, 5, 2, MicrOp.OP_NOP)
assert result == 3
+def test_compunit_fsm():
+
+ m = Module()
+ alu = Shifter(8)
+ dut = MultiCompUnit(8, alu, CompFSMOpSubset)
+ m.submodules.cu = dut
+
+ vl = rtlil.convert(dut, ports=dut.ports())
+ with open("test_compunit_fsm1.il", "w") as f:
+ f.write(vl)
+
+ sim = Simulator(m)
+ sim.add_clock(1e-6)
+
+ sim.add_sync_process(wrap(scoreboard_sim_fsm(dut)))
+ sim_writer = sim.write_vcd('test_compunit_fsm1.vcd')
+ with sim_writer:
+ sim.run()
+
+
def test_compunit():
m = Module()
with open("test_compunit1.il", "w") as f:
f.write(vl)
- run_simulation(m, scoreboard_sim(dut), vcd_name='test_compunit1.vcd')
+ sim = Simulator(m)
+ sim.add_clock(1e-6)
+
+ sim.add_sync_process(wrap(scoreboard_sim(dut)))
+ sim_writer = sim.write_vcd('test_compunit1.vcd')
+ with sim_writer:
+ sim.run()
class CompUnitParallelTest:
def driver(self):
print("Begin parallel test.")
- yield from self.operation(5, 2, InternalOp.OP_NOP, inv_a=0,
- imm=8, imm_ok=0, rdmaskn=(1, 0))
+ yield from self.operation(5, 2, MicrOp.OP_ADD)
def operation(self, a, b, op, inv_a=0, imm=0, imm_ok=0, zero_a=0,
rdmaskn=(0, 0)):
# at the same time, present the operation
yield self.dut.oper_i.insn_type.eq(self.op)
- yield self.dut.oper_i.invert_a.eq(self.inv_a)
+ yield self.dut.oper_i.invert_in.eq(self.inv_a)
yield self.dut.oper_i.imm_data.imm.eq(self.imm)
yield self.dut.oper_i.imm_data.imm_ok.eq(self.imm_ok)
yield self.dut.oper_i.zero_a.eq(self.zero_a)
# note: rdmaskn must be held, while busy_o is active
# TODO: deactivate rdmaskn when the busy_o cycle ends
yield self.dut.oper_i.insn_type.eq(0)
- yield self.dut.oper_i.invert_a.eq(0)
+ yield self.dut.oper_i.invert_in.eq(0)
yield self.dut.oper_i.imm_data.imm.eq(0)
yield self.dut.oper_i.imm_data.imm_ok.eq(0)
yield self.dut.oper_i.zero_a.eq(0)
if issue_i:
break
# issue_i has not risen yet, so rd must keep low
- rel = yield self.dut.rd.rel[rd_idx]
+ rel = yield self.dut.rd.rel_o[rd_idx]
assert not rel
yield
return
# issue_i has risen. rel must rise on the next cycle
- rel = yield self.dut.rd.rel[rd_idx]
+ rel = yield self.dut.rd.rel_o[rd_idx]
assert not rel
# stall for additional cycles. Check that rel doesn't fall on its own
for n in range(self.RD_GO_DELAY[rd_idx]):
yield
- rel = yield self.dut.rd.rel[rd_idx]
+ rel = yield self.dut.rd.rel_o[rd_idx]
assert rel
# Before asserting "go", make sure "rel" has risen.
# The use of Settle allows "go" to be set combinatorially,
# rising on the same cycle as "rel".
yield Settle()
- rel = yield self.dut.rd.rel[rd_idx]
+ rel = yield self.dut.rd.rel_o[rd_idx]
assert rel
# assert go for one cycle, passing along the operand value
- yield self.dut.rd.go[rd_idx].eq(1)
+ yield self.dut.rd.go_i[rd_idx].eq(1)
yield self.dut.src_i[rd_idx].eq(self.operands[rd_idx])
# check that the operand was sent to the alu
# TODO: Properly check the alu protocol
yield
# rel must keep high, since go was inactive in the last cycle
- rel = yield self.dut.rd.rel[rd_idx]
+ rel = yield self.dut.rd.rel_o[rd_idx]
assert rel
# finish the go one-clock pulse
- yield self.dut.rd.go[rd_idx].eq(0)
+ yield self.dut.rd.go_i[rd_idx].eq(0)
yield self.dut.src_i[rd_idx].eq(0)
yield
# rel must have gone low in response to go being high
# on the previous cycle
- rel = yield self.dut.rd.rel[rd_idx]
+ rel = yield self.dut.rd.rel_o[rd_idx]
assert not rel
self.rd_complete[rd_idx] = True
# self.expected_o and assert. use dut.get_out(wr_idx) to do so.
def run_simulation(self, vcd_name):
- run_simulation(self.dut, [self.driver(),
- self.rd(0), # one read port (a)
- self.rd(1), # one read port (b)
- self.wr(0), # one write port (o)
- ],
- vcd_name=vcd_name)
+ m = Module()
+ m.submodules.cu = self.dut
+ sim = Simulator(m)
+ sim.add_clock(1e-6)
+
+ sim.add_sync_process(wrap(self.driver()))
+ sim.add_sync_process(wrap(self.rd(0)))
+ sim.add_sync_process(wrap(self.rd(1)))
+ sim.add_sync_process(wrap(self.wr(0)))
+ sim_writer = sim.write_vcd(vcd_name)
+ with sim_writer:
+ sim.run()
+
+
+def test_compunit_regspec2_fsm():
+
+ inspec = [('INT', 'a', '0:15'),
+ ('INT', 'b', '0:15'),
+ ]
+ outspec = [('INT', 'o', '0:15'),
+ ]
+
+ regspec = (inspec, outspec)
+
+ m = Module()
+ alu = Shifter(8)
+ dut = MultiCompUnit(regspec, alu, CompFSMOpSubset)
+ m.submodules.cu = dut
+
+ sim = Simulator(m)
+ sim.add_clock(1e-6)
+
+ sim.add_sync_process(wrap(scoreboard_sim_fsm(dut)))
+ sim_writer = sim.write_vcd('test_compunit_regspec2_fsm.vcd')
+ with sim_writer:
+ sim.run()
def test_compunit_regspec3():
('INT', 'b', '0:15'),
('INT', 'c', '0:15')]
outspec = [('INT', 'o', '0:15'),
- ]
+ ]
regspec = (inspec, outspec)
dut = MultiCompUnit(regspec, alu, CompALUOpSubset)
m.submodules.cu = dut
- run_simulation(m, scoreboard_sim_dummy(dut),
- vcd_name='test_compunit_regspec3.vcd')
+ sim = Simulator(m)
+ sim.add_clock(1e-6)
+
+ sim.add_sync_process(wrap(scoreboard_sim_dummy(dut)))
+ sim_writer = sim.write_vcd('test_compunit_regspec3.vcd')
+ with sim_writer:
+ sim.run()
def test_compunit_regspec1():
inspec = [('INT', 'a', '0:15'),
('INT', 'b', '0:15')]
outspec = [('INT', 'o', '0:15'),
- ]
+ ]
regspec = (inspec, outspec)
with open("test_compunit_regspec1.il", "w") as f:
f.write(vl)
- run_simulation(m, scoreboard_sim(dut),
- vcd_name='test_compunit_regspec1.vcd')
+ sim = Simulator(m)
+ sim.add_clock(1e-6)
+
+ sim.add_sync_process(wrap(scoreboard_sim(dut)))
+ sim_writer = sim.write_vcd('test_compunit_regspec1.vcd')
+ with sim_writer:
+ sim.run()
test = CompUnitParallelTest(dut)
test.run_simulation("test_compunit_parallel.vcd")
if __name__ == '__main__':
test_compunit()
+ test_compunit_fsm()
test_compunit_regspec1()
test_compunit_regspec3()
projects / soc.git / blobdiff