Documented at http://libre-soc.org/3d_gpu/architecture/compunit
"""
+from soc.experiment.alu_fsm import Shifter, CompFSMOpSubset
+from soc.fu.alu.alu_input_record import CompALUOpSubset
+from soc.experiment.alu_hier import ALU, DummyALU
+from soc.experiment.compalu_multi import MultiCompUnit
+from soc.decoder.power_enums import MicrOp
+from nmigen import Module
+from nmigen.cli import rtlil
cxxsim = False
if cxxsim:
from nmigen.sim.cxxsim import Simulator, Settle
else:
from nmigen.back.pysim import Simulator, Settle
-from nmigen.cli import rtlil
-from nmigen import Module
-
-from soc.decoder.power_enums import MicrOp
-
-from soc.experiment.compalu_multi import MultiCompUnit
-from soc.experiment.alu_hier import ALU, DummyALU
-from soc.fu.alu.alu_input_record import CompALUOpSubset
-from soc.experiment.alu_fsm import Shifter, CompFSMOpSubset
def wrap(process):
def wrapper():
def op_sim_fsm(dut, a, b, direction):
- print ("op_sim_fsm", a, b, direction)
+ print("op_sim_fsm", a, b, direction)
yield dut.issue_i.eq(0)
yield
yield dut.src_i[0].eq(a)
yield dut.issue_i.eq(0)
yield
- yield dut.rd.go.eq(0b11)
+ yield dut.rd.go_i.eq(0b11)
while True:
yield
- rd_rel_o = yield dut.rd.rel
- print ("rd_rel", rd_rel_o)
+ rd_rel_o = yield dut.rd.rel_o
+ print("rd_rel", rd_rel_o)
if rd_rel_o:
break
- yield dut.rd.go.eq(0)
+ yield dut.rd.go_i.eq(0)
- req_rel_o = yield dut.wr.rel
+ req_rel_o = yield dut.wr.rel_o
result = yield dut.data_o
- print ("req_rel", req_rel_o, result)
+ print("req_rel", req_rel_o, result)
while True:
- req_rel_o = yield dut.wr.rel
+ req_rel_o = yield dut.wr.rel_o
result = yield dut.data_o
- print ("req_rel", req_rel_o, result)
+ print("req_rel", req_rel_o, result)
if req_rel_o:
break
yield
- yield dut.wr.go[0].eq(1)
+ yield dut.wr.go_i[0].eq(1)
yield Settle()
result = yield dut.data_o
yield
- print ("result", result)
- yield dut.wr.go[0].eq(0)
+ print("result", result)
+ yield dut.wr.go_i[0].eq(0)
yield
return result
yield dut.src_i[0].eq(a)
yield dut.src_i[1].eq(b)
yield dut.oper_i.insn_type.eq(op)
- yield dut.oper_i.invert_a.eq(inv_a)
+ yield dut.oper_i.invert_in.eq(inv_a)
yield dut.oper_i.imm_data.imm.eq(imm)
yield dut.oper_i.imm_data.imm_ok.eq(imm_ok)
yield dut.oper_i.zero_a.eq(zero_a)
yield dut.issue_i.eq(0)
yield
if not imm_ok or not zero_a:
- yield dut.rd.go.eq(0b11)
+ yield dut.rd.go_i.eq(0b11)
while True:
yield
- rd_rel_o = yield dut.rd.rel
- print ("rd_rel", rd_rel_o)
+ rd_rel_o = yield dut.rd.rel_o
+ print("rd_rel", rd_rel_o)
if rd_rel_o:
break
- yield dut.rd.go.eq(0)
+ yield dut.rd.go_i.eq(0)
else:
- print ("no go rd")
+ print("no go rd")
if len(dut.src_i) == 3:
- yield dut.rd.go.eq(0b100)
+ yield dut.rd.go_i.eq(0b100)
while True:
yield
- rd_rel_o = yield dut.rd.rel
- print ("rd_rel", rd_rel_o)
+ rd_rel_o = yield dut.rd.rel_o
+ print("rd_rel", rd_rel_o)
if rd_rel_o:
break
- yield dut.rd.go.eq(0)
+ yield dut.rd.go_i.eq(0)
else:
- print ("no 3rd rd")
+ print("no 3rd rd")
- req_rel_o = yield dut.wr.rel
+ req_rel_o = yield dut.wr.rel_o
result = yield dut.data_o
- print ("req_rel", req_rel_o, result)
+ print("req_rel", req_rel_o, result)
while True:
- req_rel_o = yield dut.wr.rel
+ req_rel_o = yield dut.wr.rel_o
result = yield dut.data_o
- print ("req_rel", req_rel_o, result)
+ print("req_rel", req_rel_o, result)
if req_rel_o:
break
yield
- yield dut.wr.go[0].eq(1)
+ yield dut.wr.go_i[0].eq(1)
yield Settle()
result = yield dut.data_o
yield
- print ("result", result)
- yield dut.wr.go[0].eq(0)
+ print("result", result)
+ yield dut.wr.go_i[0].eq(0)
yield
return result
def scoreboard_sim_dummy(dut):
result = yield from op_sim(dut, 5, 2, MicrOp.OP_NOP, inv_a=0,
- imm=8, imm_ok=1)
+ imm=8, imm_ok=1)
assert result == 5, result
result = yield from op_sim(dut, 9, 2, MicrOp.OP_NOP, inv_a=0,
- imm=8, imm_ok=1)
+ imm=8, imm_ok=1)
assert result == 9, result
-
def scoreboard_sim(dut):
# zero (no) input operands test
result = yield from op_sim(dut, 5, 2, MicrOp.OP_ADD, zero_a=1,
- imm=8, imm_ok=1)
+ imm=8, imm_ok=1)
assert result == 8
result = yield from op_sim(dut, 5, 2, MicrOp.OP_ADD, inv_a=0,
- imm=8, imm_ok=1)
+ imm=8, imm_ok=1)
assert result == 13
result = yield from op_sim(dut, 5, 2, MicrOp.OP_ADD)
# at the same time, present the operation
yield self.dut.oper_i.insn_type.eq(self.op)
- yield self.dut.oper_i.invert_a.eq(self.inv_a)
+ yield self.dut.oper_i.invert_in.eq(self.inv_a)
yield self.dut.oper_i.imm_data.imm.eq(self.imm)
yield self.dut.oper_i.imm_data.imm_ok.eq(self.imm_ok)
yield self.dut.oper_i.zero_a.eq(self.zero_a)
# note: rdmaskn must be held, while busy_o is active
# TODO: deactivate rdmaskn when the busy_o cycle ends
yield self.dut.oper_i.insn_type.eq(0)
- yield self.dut.oper_i.invert_a.eq(0)
+ yield self.dut.oper_i.invert_in.eq(0)
yield self.dut.oper_i.imm_data.imm.eq(0)
yield self.dut.oper_i.imm_data.imm_ok.eq(0)
yield self.dut.oper_i.zero_a.eq(0)
if issue_i:
break
# issue_i has not risen yet, so rd must keep low
- rel = yield self.dut.rd.rel[rd_idx]
+ rel = yield self.dut.rd.rel_o[rd_idx]
assert not rel
yield
return
# issue_i has risen. rel must rise on the next cycle
- rel = yield self.dut.rd.rel[rd_idx]
+ rel = yield self.dut.rd.rel_o[rd_idx]
assert not rel
# stall for additional cycles. Check that rel doesn't fall on its own
for n in range(self.RD_GO_DELAY[rd_idx]):
yield
- rel = yield self.dut.rd.rel[rd_idx]
+ rel = yield self.dut.rd.rel_o[rd_idx]
assert rel
# Before asserting "go", make sure "rel" has risen.
# The use of Settle allows "go" to be set combinatorially,
# rising on the same cycle as "rel".
yield Settle()
- rel = yield self.dut.rd.rel[rd_idx]
+ rel = yield self.dut.rd.rel_o[rd_idx]
assert rel
# assert go for one cycle, passing along the operand value
- yield self.dut.rd.go[rd_idx].eq(1)
+ yield self.dut.rd.go_i[rd_idx].eq(1)
yield self.dut.src_i[rd_idx].eq(self.operands[rd_idx])
# check that the operand was sent to the alu
# TODO: Properly check the alu protocol
yield
# rel must keep high, since go was inactive in the last cycle
- rel = yield self.dut.rd.rel[rd_idx]
+ rel = yield self.dut.rd.rel_o[rd_idx]
assert rel
# finish the go one-clock pulse
- yield self.dut.rd.go[rd_idx].eq(0)
+ yield self.dut.rd.go_i[rd_idx].eq(0)
yield self.dut.src_i[rd_idx].eq(0)
yield
# rel must have gone low in response to go being high
# on the previous cycle
- rel = yield self.dut.rd.rel[rd_idx]
+ rel = yield self.dut.rd.rel_o[rd_idx]
assert not rel
self.rd_complete[rd_idx] = True
inspec = [('INT', 'a', '0:15'),
('INT', 'b', '0:15'),
- ]
- outspec = [('INT', 'o', '0:15'),
]
+ outspec = [('INT', 'o', '0:15'),
+ ]
regspec = (inspec, outspec)
('INT', 'b', '0:15'),
('INT', 'c', '0:15')]
outspec = [('INT', 'o', '0:15'),
- ]
+ ]
regspec = (inspec, outspec)
inspec = [('INT', 'a', '0:15'),
('INT', 'b', '0:15')]
outspec = [('INT', 'o', '0:15'),
- ]
+ ]
regspec = (inspec, outspec)
projects / soc.git / blobdiff