Add GTKWave document to test_compunit_fsm

[soc.git] / src / soc / experiment / test / test_compalu_multi.py

diff --git a/src/soc/experiment/test/test_compalu_multi.py b/src/soc/experiment/test/test_compalu_multi.py
index 97eb635f2f2c59d6a722c898b2bd6a3ac49a26a2..fc21db82ee9ea77b1cf31f2d6c2f704c4346de1c 100644 (file)
--- a/src/soc/experiment/test/test_compalu_multi.py
+++ b/src/soc/experiment/test/test_compalu_multi.py
@@ -15,13 +15,13 @@ from soc.fu.alu.alu_input_record import CompALUOpSubset
 from soc.experiment.alu_hier import ALU, DummyALU
 from soc.experiment.compalu_multi import MultiCompUnit
 from soc.decoder.power_enums import MicrOp
+from nmutil.gtkw import write_gtkw
 from nmigen import Module
 from nmigen.cli import rtlil
-cxxsim = False
-if cxxsim:
-    from nmigen.sim.cxxsim import Simulator, Settle
-else:
-    from nmigen.back.pysim import Simulator, Settle
+
+# NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
+# Also, check out the cxxsim nmigen branch, and latest yosys from git
+from nmutil.sim_tmp_alternative import Simulator, Settle, is_engine_pysim
 
 
 def wrap(process):
@@ -78,8 +78,8 @@ def op_sim(dut, a, b, op, inv_a=0, imm=0, imm_ok=0, zero_a=0):
     yield dut.src_i[1].eq(b)
     yield dut.oper_i.insn_type.eq(op)
     yield dut.oper_i.invert_in.eq(inv_a)
-    yield dut.oper_i.imm_data.imm.eq(imm)
-    yield dut.oper_i.imm_data.imm_ok.eq(imm_ok)
+    yield dut.oper_i.imm_data.data.eq(imm)
+    yield dut.oper_i.imm_data.ok.eq(imm_ok)
     yield dut.oper_i.zero_a.eq(zero_a)
     yield dut.issue_i.eq(1)
     yield
@@ -177,7 +177,24 @@ def scoreboard_sim(dut):
 
 
 def test_compunit_fsm():
-
+    top = "top.cu" if is_engine_pysim() else "cu"
+    traces = [
+        'clk', 'src1_i[7:0]', 'src2_i[7:0]', 'oper_i_None__sdir', 'cu_issue_i',
+        'cu_busy_o', 'cu_rd__rel_o[1:0]', 'cu_rd__go_i[1:0]',
+        'cu_wr__rel_o', 'cu_wr__go_i', 'dest1_o[7:0]',
+        ('alu', {'module': top+'.alu'}, [
+            'p_data_i[7:0]', 'p_shift_i[7:0]', 'op__sdir',
+            'p_valid_i', 'p_ready_o', 'n_valid_o', 'n_ready_i',
+            'n_data_o[7:0]'
+        ])
+
+    ]
+    write_gtkw(
+        "test_compunit_fsm1.gtkw",
+        "test_compunit_fsm1.vcd",
+        traces,
+        module=top
+    )
     m = Module()
     alu = Shifter(8)
     dut = MultiCompUnit(8, alu, CompFSMOpSubset)
@@ -286,8 +303,8 @@ class CompUnitParallelTest:
         # at the same time, present the operation
         yield self.dut.oper_i.insn_type.eq(self.op)
         yield self.dut.oper_i.invert_in.eq(self.inv_a)
-        yield self.dut.oper_i.imm_data.imm.eq(self.imm)
-        yield self.dut.oper_i.imm_data.imm_ok.eq(self.imm_ok)
+        yield self.dut.oper_i.imm_data.data.eq(self.imm)
+        yield self.dut.oper_i.imm_data.ok.eq(self.imm_ok)
         yield self.dut.oper_i.zero_a.eq(self.zero_a)
         rdmaskn = self.rdmaskn[0] | (self.rdmaskn[1] << 1)
         yield self.dut.rdmaskn.eq(rdmaskn)
@@ -311,8 +328,8 @@ class CompUnitParallelTest:
         # TODO: deactivate rdmaskn when the busy_o cycle ends
         yield self.dut.oper_i.insn_type.eq(0)
         yield self.dut.oper_i.invert_in.eq(0)
-        yield self.dut.oper_i.imm_data.imm.eq(0)
-        yield self.dut.oper_i.imm_data.imm_ok.eq(0)
+        yield self.dut.oper_i.imm_data.data.eq(0)
+        yield self.dut.oper_i.imm_data.ok.eq(0)
         yield self.dut.oper_i.zero_a.eq(0)
         yield