Merge branch 'master' of ssh://git.libre-riscv.org:922/soc

[soc.git] / src / soc / experiment / test / test_loadstore1.py

diff --git a/src/soc/experiment/test/test_loadstore1.py b/src/soc/experiment/test/test_loadstore1.py
index 377403d10a3b98104040fe541898649fe2f7eb2b..64c3b6c61e5b8958a77b387633d7144b838f0b0a 100644 (file)
--- a/src/soc/experiment/test/test_loadstore1.py
+++ b/src/soc/experiment/test/test_loadstore1.py
@@ -8,7 +8,8 @@ from random import randint, seed
 from nmigen.sim import Simulator, Delay, Settle
 from nmutil.util import wrap
 
-from soc.config.test.test_pi2ls import pi_ld, pi_st, pi_ldst, wait_busy
+from soc.config.test.test_pi2ls import (pi_ld, pi_st, pi_ldst, wait_busy,
+                                        get_exception_info)
 #from soc.config.test.test_pi2ls import pi_st_debug
 from soc.config.test.test_loadstore import TestMemPspec
 from soc.config.loadstore import ConfigMemoryPortInterface
@@ -191,9 +192,11 @@ def _test_loadstore1_ifetch(dut, mem):
     yield ldst.instr_fault.eq(0)
     while True:
         done = yield (ldst.done)
-        if done:
+        exc_info = yield from get_exception_info(pi.exc_o)
+        if done or exc_info.happened:
             break
         yield
+    assert exc_info.happened == 0 # assert just before doing the fault set zero
     yield ldst.instr_fault.eq(0)
     yield
     yield