from openpower.test import wb_get as wbget
from openpower.exceptions import LDSTExceptionTuple
+from soc.config.test.test_fetch import read_from_addr
+from openpower.decoder.power_enums import MSRSpec
+
def setup_mmu():
icache = dut.submodules.ldst.icache
wbget.stop = False
-
print("=== test loadstore instruction (real) ===")
i_in = icache.i_in
i_m_in = icache.m_in
yield from debug(dut, "real mem instruction")
- # set address to zero, update mem[0] to 01234
+ # set address to 0x8, update mem[0x8] to 01234 | 0x5678<<32
+ # (have to do 64-bit writes into the dictionary-memory-emulated-thing)
addr = 8
+ addr2 = 12
+ expected_insn2 = 0x5678
expected_insn = 0x1234
- mem[addr] = expected_insn
+ mem[addr] = expected_insn | expected_insn2<<32
yield i_in.priv_mode.eq(1)
- yield i_in.req.eq(0) # NO, must use FetchUnitInterface
- yield i_in.nia.eq(addr) # NO, must use FetchUnitInterface
- yield i_in.stop_mark.eq(0) # NO, must use FetchUnitInterface
- yield i_m_in.tlbld.eq(0)
- yield i_m_in.tlbie.eq(0)
- yield i_m_in.addr.eq(0)
- yield i_m_in.pte.eq(0)
- yield
- yield
- yield
-
- # miss, stalls for a bit -- this one is different here
- ##nia, insn, valid, failed = yield from icache_read(dut,addr,0,0)
- ##assert(valid==0)
- ##assert(failed==1)
-
- yield i_in.req.eq(1) # NO, must use FetchUnitInterface
- yield i_in.nia.eq(addr) # NO, must use FetchUnitInterface
- yield
- valid = yield i_out.valid # NO, must use FetchUnitInterface
- while not valid: # NO, must use FetchUnitInterface
- yield # NO, must use FetchUnitInterface
- valid = yield i_out.valid # NO, must use FetchUnitInterface
- yield i_in.req.eq(0) # NO, must use FetchUnitInterface
+ insn = yield from read_from_addr(icache, addr, stall=False)
nia = yield i_out.nia # NO, must use FetchUnitInterface
- insn = yield i_out.insn # NO, must use FetchUnitInterface
- yield
- yield
-
print ("fetched %x from addr %x" % (insn, nia))
assert insn == expected_insn
+ print("=== test loadstore instruction (2nd, real) ===")
+ yield from debug(dut, "real mem 2nd (addr 0xc)")
+
+ insn2 = yield from read_from_addr(icache, addr2, stall=False)
+
+ nia = yield i_out.nia # NO, must use FetchUnitInterface
+ print ("fetched %x from addr2 %x" % (insn2, nia))
+ assert insn2 == expected_insn2
+
print("=== test loadstore instruction (done) ===")
yield from debug(dut, "test done")
yield
yield
- print ("failed?", "yes" if failed else "no")
- assert failed == 0
-
print ("fetched %x from addr %x" % (insn, nia))
assert insn == expected_insn
wbget.stop = True
def _test_loadstore1_ifetch_multi(dut, mem):
+ mmu = dut.submodules.mmu
+ ldst = dut.submodules.ldst
+ pi = ldst.pi
+ icache = dut.submodules.ldst.icache
+ wbget.stop = False
+
+ i_in = icache.i_in
+ i_out = icache.i_out
+ i_m_in = icache.m_in
+
yield from debug(dut, "TODO")
yield
yield
yield
# TODO fetch instructions from multiple addresses
# should cope with some addresses being invalid
- addrs = [0x10200,0x10204,10208,10200]
+ addrs = [0,4,8,0,0x10200,0x10204,0x10208,0x10200]
+
+ mem[0x10200]=0xFF00FF00EE00EE00EE
+ mem[0]=0xFF00FF00EE00EE00EE
+
+ yield i_in.priv_mode.eq(1)
+
for addr in addrs:
- yield from debug(dut, "TODO_fetch_from "+hex(addrs))
+ yield from debug(dut, "BROKEN_fetch_from "+hex(addr))
# use the new interface in this test
- yield
- yield
- yield
+
+ #broken: does not use wishbone yet - investigate
+ insn = yield from read_from_addr(icache, addr, stall=False)
+
+ nia = yield i_out.nia # NO, must use FetchUnitInterface
+ print ("TEST_MULTI: fetched %x from addr %x == %x" % (insn, nia,addr))
+
+ wbget.stop = True
def _test_loadstore1_ifetch(dut, mem):
"""test_loadstore1_ifetch
yield ldst.priv_mode.eq(0)
yield ldst.instr_fault.eq(1)
yield ldst.maddr.eq(virt_addr)
- #ld_data, exctype, exc = yield from pi_ld(pi, virt_addr, 8, msr_pr=1)
+ # still broken -- investigate
+ # msr = MSRSpec(pr=?, dr=?, sf=0)
+ # ld_data, exctype, exc = yield from pi_ld(pi, virt_addr, 8, msr=msr)
yield
yield ldst.instr_fault.eq(0)
while True:
print("=== test invalid ===")
addr = 0
- ld_data, exctype, exc = yield from pi_ld(pi, addr, 8, msr_pr=1)
+ msr = MSRSpec(pr=1, dr=0, sf=0) # set problem-state
+ ld_data, exctype, exc = yield from pi_ld(pi, addr, 8, msr=msr)
print("ld_data", ld_data, exctype, exc)
assert (exctype == "slow")
invalid = exc.invalid
data = 0xf553b658ba7e1f51
if test_dcbz:
- yield from pi_st(pi, addr, data, 8, msr_pr=1)
+ msr = MSRSpec(pr=0, dr=0, sf=0)
+ yield from pi_st(pi, addr, data, 8, msr=msr)
yield
- ld_data, exctype, exc = yield from pi_ld(pi, addr, 8, msr_pr=1)
+ ld_data, exctype, exc = yield from pi_ld(pi, addr, 8, msr=msr)
assert ld_data == 0xf553b658ba7e1f51
assert exctype is None
- ld_data, exctype, exc = yield from pi_ld(pi, addr, 8, msr_pr=1)
+ ld_data, exctype, exc = yield from pi_ld(pi, addr, 8, msr=msr)
assert ld_data == 0xf553b658ba7e1f51
assert exctype is None
print("do_dcbz ===============")
- yield from pi_st(pi, addr, data, 8, msr_pr=1, is_dcbz=1)
+ yield from pi_st(pi, addr, data, 8, msr=msr, is_dcbz=1)
print("done_dcbz ===============")
yield
- ld_data, exctype, exc = yield from pi_ld(pi, addr, 8, msr_pr=1)
+ ld_data, exctype, exc = yield from pi_ld(pi, addr, 8, msr=msr)
print("ld_data after dcbz")
print(ld_data)
assert ld_data == 0
if test_exceptions:
print("=== alignment error (ld) ===")
addr = 0xFF100e0FF
- ld_data, exctype, exc = yield from pi_ld(pi, addr, 8, msr_pr=1)
+ ld_data, exctype, exc = yield from pi_ld(pi, addr, 8, msr=msr)
if exc:
alignment = exc.alignment
happened = exc.happened
print("=== alignment error (st) ===")
addr = 0xFF100e0FF
- exctype, exc = yield from pi_st(pi, addr,0, 8, msr_pr=1)
+ exctype, exc = yield from pi_st(pi, addr,0, 8, msr=msr)
if exc:
alignment = exc.alignment
happened = exc.happened
if True:
print("=== no alignment error (ld) ===")
addr = 0x100e0
- ld_data, exctype, exc = yield from pi_ld(pi, addr, 8, msr_pr=1)
+ ld_data, exctype, exc = yield from pi_ld(pi, addr, 8, msr=msr)
print("ld_data", ld_data, exctype, exc)
if exc:
alignment = exc.alignment
for addr in addrs:
print("== RANDOM addr ==",hex(addr))
- ld_data, exctype, exc = yield from pi_ld(pi, addr, 8, msr_pr=1)
+ ld_data, exctype, exc = yield from pi_ld(pi, addr, 8, msr=msr)
print("ld_data[RANDOM]",ld_data,exc,addr)
assert (exctype == None)
for addr in addrs:
print("== RANDOM addr ==",hex(addr))
- exc = yield from pi_st(pi, addr,0xFF*addr, 8, msr_pr=1)
+ exc = yield from pi_st(pi, addr,0xFF*addr, 8, msr=msr)
assert (exctype == None)
# readback written data and compare
for addr in addrs:
print("== RANDOM addr ==",hex(addr))
- ld_data, exctype, exc = yield from pi_ld(pi, addr, 8, msr_pr=1)
+ ld_data, exctype, exc = yield from pi_ld(pi, addr, 8, msr=msr)
print("ld_data[RANDOM_READBACK]",ld_data,exc,addr)
assert (exctype == None)
assert (ld_data == 0xFF*addr)
yield ldst.priv_mode.eq(0)
yield ldst.instr_fault.eq(1)
yield ldst.maddr.eq(virt_addr)
- #ld_data, exctype, exc = yield from pi_ld(pi, virt_addr, 8, msr_pr=1)
+ #ld_data, exctype, exc = yield from pi_ld(pi, virt_addr, 8, msr=msr)
yield
yield ldst.instr_fault.eq(0)
while True:
mem = pagetables.test1
- # nmigen Simulation
- sim = Simulator(m)
- sim.add_clock(1e-6)
-
+ # set this up before passing to Simulator (which calls elaborate)
icache = m.submodules.ldst.icache
icache.use_fetch_interface() # this is the function which converts
# to FetchUnitInterface. *including*
# rewiring the Wishbone Bus to ibus
+
+ # nmigen Simulation
+ sim = Simulator(m)
+ sim.add_clock(1e-6)
+
sim.add_sync_process(wrap(_test_loadstore1_ifetch_iface(m, mem)))
# add two wb_get processes onto the *same* memory dictionary.
# this shouuuld work.... cross-fingers...
sim.add_clock(1e-6)
icache = m.submodules.ldst.icache
+ icache.use_fetch_interface() # see test_loadstore1_ifetch_unit_iface():
+
sim.add_sync_process(wrap(_test_loadstore1_ifetch_multi(m, mem)))
# add two wb_get processes onto the *same* memory dictionary.
# this shouuuld work.... cross-fingers...
sim.add_sync_process(wrap(wb_get(cmpi.wb_bus(), mem)))
- sim.add_sync_process(wrap(wb_get(icache.bus, mem)))
+ sim.add_sync_process(wrap(wb_get(icache.ibus, mem))) # ibus not bus
with sim.write_vcd('test_loadstore1_ifetch_multi.vcd',
traces=[m.debug_status]): # include extra debug
sim.run()
if __name__ == '__main__':
test_loadstore1()
test_loadstore1_invalid()
- test_loadstore1_ifetch()
- test_loadstore1_fetch_unit_iface()
+ test_loadstore1_ifetch() #FIXME
test_loadstore1_ifetch_invalid()
test_loadstore1_ifetch_multi()
-
+ test_loadstore1_ifetch_unit_iface()
projects / soc.git / blobdiff