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[soc.git] / src / soc / experiment / testmem.py

diff --git a/src/soc/experiment/testmem.py b/src/soc/experiment/testmem.py
index 02000d89e375f830a1760c13ef818f68cfc1287d..12b04915e764302f5920ef6e667c140be5daf034 100644 (file)
--- a/src/soc/experiment/testmem.py
+++ b/src/soc/experiment/testmem.py
@@ -2,30 +2,38 @@ from nmigen import Module, Elaboratable, Memory
 
 
 class TestMemory(Elaboratable):
-    def __init__(self, regwid, addrw, granularity=None, init=True):
-        self.ddepth = 1 # regwid //8
-        depth = (1<<addrw) // self.ddepth
+    def __init__(self, regwid, addrw, granularity=None, init=True,
+                 readonly=False):
+        self.readonly = readonly
+        self.ddepth = 1  # regwid //8
+        depth = (1 << addrw) // self.ddepth
         self.depth = depth
         self.regwid = regwid
-        print ("test memory", regwid, depth)
+        print("test memory width depth", regwid, depth)
         if init is True:
             init = range(0, depth*2, 2)
         else:
             init = None
         self.mem = Memory(width=regwid, depth=depth, init=init)
-        self.rdport = self.mem.read_port() # not now transparent=False)
+        self.rdport = self.mem.read_port()  # not now transparent=False)
+        if self.readonly:
+            return
         self.wrport = self.mem.write_port(granularity=granularity)
 
     def elaborate(self, platform):
         m = Module()
         m.submodules.rdport = self.rdport
+        if self.readonly:
+            return m
         m.submodules.wrport = self.wrport
         return m
 
     def __iter__(self):
         yield self.rdport.addr
         yield self.rdport.data
-        #yield self.rdport.en
+        # yield self.rdport.en
+        if self.readonly:
+            return
         yield self.wrport.addr
         yield self.wrport.data
         yield self.wrport.en