reorder / reorganise reset signals slightly

[soc.git] / src / soc / experiment / wb_types.py

diff --git a/src/soc/experiment/wb_types.py b/src/soc/experiment/wb_types.py
index 0f89871cb158c411d93984b9fa3ef8ceea840538..bcf64b4215cbe4ae044debbb6f7fe4c0ec35cd79 100644 (file)
--- a/src/soc/experiment/wb_types.py
+++ b/src/soc/experiment/wb_types.py
@@ -38,7 +38,7 @@ def WBDataType():
     return Signal(WB_DATA_BITS, name="dat")
 
 def WBSelType():
-    return Signal(WB_SEL_BITS, name="sel")
+    return Signal(WB_SEL_BITS, name="sel", reset=0b11111111)
 
 # type wishbone_master_out is record
 #     adr : wishbone_addr_type;
@@ -71,8 +71,8 @@ def WBMasterOutInit():
 #     stall : std_ulogic;
 # end record;
 class WBSlaveOut(RecordObject):
-    def __init__(self):
-        super().__init__()
+    def __init__(self, name=None):
+        super().__init__(name=name)
         self.dat   = WBDataType()
         self.ack   = Signal()
         self.stall = Signal()
@@ -104,8 +104,8 @@ def WBSlaveOutVector():
 # end record;
 # IO Bus to a device, 30-bit address, 32-bits data
 class WBIOMasterOut(RecordObject):
-    def __init__(self):
-        super().__init__()
+    def __init__(self, name=None):
+        super().__init__(name=name)
         self.adr = Signal(30)
         self.dat = Signal(32)
         self.sel = Signal(4)
@@ -119,8 +119,8 @@ class WBIOMasterOut(RecordObject):
 #     stall : std_ulogic;
 # end record;
 class WBIOSlaveOut(RecordObject):
-    def __init__(self):
-        super().__init__()
+    def __init__(self, name=None):
+        super().__init__(name=name)
         self.data  = Signal(32)
         self.ack   = Signal()
         self.stall = Signal()