"""
from nmigen import Signal
-from nmigen.iocontrol import RecordObject
+from nmutil.iocontrol import RecordObject
# library ieee;
# Main CPU bus. 32-bit address, 64-bit data
WB_ADDR_BITS = 32
WB_DATA_BITS = 64
-WB_SEL_BITS = WB_DATA_BITS / 8
+WB_SEL_BITS = WB_DATA_BITS // 8
# subtype wishbone_addr_type is
# std_ulogic_vector(wishbone_addr_bits-1 downto 0);
# std_ulogic_vector(wishbone_sel_bits-1 downto 0);
def WBAddrType():
- return Signal(WB_ADDR_BITS)
+ return Signal(WB_ADDR_BITS, name="adr")
def WBDataType():
- return Signal(WB_DATA_BITS)
+ return Signal(WB_DATA_BITS, name="dat")
def WBSelType():
- return Signal(WB_SEL_BITS)
+ return Signal(WB_SEL_BITS, name="sel", reset=0b11111111)
# type wishbone_master_out is record
# adr : wishbone_addr_type;
# we : std_ulogic;
# end record;
class WBMasterOut(RecordObject):
- def __init__(self):
- super().__init__()
+ def __init__(self, name=None):
+ super().__init__(name=name)
self.adr = WBAddrType()
self.dat = WBDataType()
self.cyc = Signal()
# stall : std_ulogic;
# end record;
class WBSlaveOut(RecordObject):
- def __init__(self):
- super().__init__()
+ def __init__(self, name=None):
+ super().__init__(name=name)
self.dat = WBDataType()
self.ack = Signal()
self.stall = Signal()
# end record;
# IO Bus to a device, 30-bit address, 32-bits data
class WBIOMasterOut(RecordObject):
- def __init__(self):
- super().__init__()
+ def __init__(self, name=None):
+ super().__init__(name=name)
self.adr = Signal(30)
self.dat = Signal(32)
self.sel = Signal(4)
# stall : std_ulogic;
# end record;
class WBIOSlaveOut(RecordObject):
- def __init__(self):
- super().__init__()
+ def __init__(self, name=None):
+ super().__init__(name=name)
self.data = Signal(32)
self.ack = Signal()
self.stall = Signal()