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rename invert_a to invert_in because logical inverts RB
[soc.git]
/
src
/
soc
/
fu
/
alu
/
alu_input_record.py
diff --git
a/src/soc/fu/alu/alu_input_record.py
b/src/soc/fu/alu/alu_input_record.py
index 0b231cfda868e1a2565282bbd4bd4b4333aa6fbd..07fdb5f716e7beb3f9fa384060f846298c82b12b 100644
(file)
--- a/
src/soc/fu/alu/alu_input_record.py
+++ b/
src/soc/fu/alu/alu_input_record.py
@@
-16,7
+16,7
@@
class CompALUOpSubset(CompOpSubsetBase):
('imm_data', Layout((("imm", 64), ("imm_ok", 1)))),
('rc', Layout((("rc", 1), ("rc_ok", 1)))), # Data
('oe', Layout((("oe", 1), ("oe_ok", 1)))), # Data
- ('invert_
a
', 1),
+ ('invert_
in
', 1),
('zero_a', 1),
('invert_out', 1),
('write_cr0', 1),