rename invert_a to invert_in because logical inverts RB

[soc.git] / src / soc / fu / alu / alu_input_record.py

diff --git a/src/soc/fu/alu/alu_input_record.py b/src/soc/fu/alu/alu_input_record.py
index 70e4a9c273a5c1718a177b470d525257b00c4d29..07fdb5f716e7beb3f9fa384060f846298c82b12b 100644 (file)
--- a/src/soc/fu/alu/alu_input_record.py
+++ b/src/soc/fu/alu/alu_input_record.py
@@ -1,9 +1,9 @@
-from nmigen.hdl.rec import Record, Layout
+from soc.fu.base_input_record import CompOpSubsetBase
+from soc.decoder.power_enums import MicrOp, Function, CryIn
+from nmigen.hdl.rec import Layout
 
-from soc.decoder.power_enums import InternalOp, Function, CryIn
 
-
-class CompALUOpSubset(Record):
+class CompALUOpSubset(CompOpSubsetBase):
     """CompALUOpSubset
 
     a copy of the relevant subset information from Decode2Execute1Type
@@ -11,12 +11,12 @@ class CompALUOpSubset(Record):
     grab subsets.
     """
     def __init__(self, name=None):
-        layout = (('insn_type', InternalOp),
+        layout = (('insn_type', MicrOp),
                   ('fn_unit', Function),
                   ('imm_data', Layout((("imm", 64), ("imm_ok", 1)))),
                   ('rc', Layout((("rc", 1), ("rc_ok", 1)))), # Data
                   ('oe', Layout((("oe", 1), ("oe_ok", 1)))), # Data
-                  ('invert_a', 1),
+                  ('invert_in', 1),
                   ('zero_a', 1),
                   ('invert_out', 1),
                   ('write_cr0', 1),
@@ -27,37 +27,5 @@ class CompALUOpSubset(Record):
                   ('data_len', 4), # actually used by ALU, in OP_EXTS
                   ('insn', 32),
                   )
+        super().__init__(layout, name=name)
 
-        Record.__init__(self, Layout(layout), name=name)
-
-        # grrr.  Record does not have kwargs
-        self.insn_type.reset_less = True
-        self.fn_unit.reset_less = True
-        self.zero_a.reset_less = True
-        self.invert_a.reset_less = True
-        self.invert_out.reset_less = True
-        self.input_carry.reset_less = True
-        self.output_carry.reset_less = True
-        self.is_32bit.reset_less = True
-        self.is_signed.reset_less = True
-        self.data_len.reset_less = True
-
-    def eq_from_execute1(self, other):
-        """ use this to copy in from Decode2Execute1Type
-        """
-        res = []
-        for fname, sig in self.fields.items():
-            eqfrom = other.do.fields[fname]
-            res.append(sig.eq(eqfrom))
-        return res
-
-    def ports(self):
-        return [self.insn_type,
-                self.invert_a,
-                self.invert_out,
-                self.input_carry,
-                self.output_carry,
-                self.is_32bit,
-                self.is_signed,
-                self.data_len,
-        ]