move over to from openpower imports

[soc.git] / src / soc / fu / alu / formal / proof_output_stage.py

diff --git a/src/soc/fu/alu/formal/proof_output_stage.py b/src/soc/fu/alu/formal/proof_output_stage.py
index 7dd3f3833553c75e4536b4b2ff70f94c00d45f7f..5e32fbfde9d84e0c91dbf5a0171edae5a95f9f7d 100644 (file)
--- a/src/soc/fu/alu/formal/proof_output_stage.py
+++ b/src/soc/fu/alu/formal/proof_output_stage.py
@@ -15,7 +15,7 @@ from nmigen.cli import rtlil
 from soc.fu.alu.output_stage import ALUOutputStage
 from soc.fu.alu.pipe_data import ALUPipeSpec
 from soc.fu.alu.alu_input_record import CompALUOpSubset
-from soc.decoder.power_enums import MicrOp
+from openpower.decoder.power_enums import MicrOp
 import unittest