Handle carry out in alu

[soc.git] / src / soc / fu / alu / output_stage.py

diff --git a/src/soc/fu/alu/output_stage.py b/src/soc/fu/alu/output_stage.py
index 20f00d6e55a875c1ac5eb4b6fcb20ad26f3dcbd0..24a47ce7179a73b82c7fba848ca6901bdd70a95d 100644 (file)
--- a/src/soc/fu/alu/output_stage.py
+++ b/src/soc/fu/alu/output_stage.py
@@ -37,6 +37,10 @@ class ALUOutputStage(PipeModBase):
         with m.Else():
             comb += target.eq(o)
 
+        # Handle carry_out
+        with m.If(self.i.ctx.op.output_carry):
+            comb += self.o.carry_out.eq(self.i.carry_out)
+
         # create condition register cr0 and sticky-overflow
         is_zero = Signal(reset_less=True)
         is_positive = Signal(reset_less=True)