bit of a big reorg of data structures

[soc.git] / src / soc / fu / alu / output_stage.py

diff --git a/src/soc/fu/alu/output_stage.py b/src/soc/fu/alu/output_stage.py
index 44c90a375b69882505ceb5744de146295210133a..2cf8c3251cbeaf53eb12f975d11571a7317d65d6 100644 (file)
--- a/src/soc/fu/alu/output_stage.py
+++ b/src/soc/fu/alu/output_stage.py
@@ -27,7 +27,7 @@ class ALUOutputStage(CommonOutputStage):
         # are actually required (oe enabled/set) otherwise the CompALU
         # can (will) ignore them.
         oe = Signal(reset_less=True)
-        comb += oe.eq(op.oe.oe & op.oe.oe_ok)
+        comb += oe.eq(op.oe.oe & op.oe.ok)
         with m.If(oe):
             # XXX see https://bugs.libre-soc.org/show_bug.cgi?id=319#c5
             comb += xer_so_o.data.eq(xer_so_i[0] | xer_ov_i[0]) # SO