ALU output stage, change logic slightly

[soc.git] / src / soc / fu / alu / output_stage.py

diff --git a/src/soc/fu/alu/output_stage.py b/src/soc/fu/alu/output_stage.py
index 98e653a5321e6aa6258187375394152f8a62a2a7..3ea71b56f72e0a69607a1dc463d02d658a56d54e 100644 (file)
--- a/src/soc/fu/alu/output_stage.py
+++ b/src/soc/fu/alu/output_stage.py
@@ -28,9 +28,10 @@ class ALUOutputStage(CommonOutputStage):
         # copy overflow and sticky-overflow.  indicate to CompALU if they
         # are actually required (oe enabled/set) otherwise the CompALU
         # can (will) ignore them.
-        comb += self.o.xer_so.data.eq(self.so)
-        comb += self.o.xer_so.ok.eq(op.oe.oe & op.oe.oe_ok)
-        comb += self.o.xer_ov.data.eq(xer_ov_i)
-        comb += self.o.xer_ov.ok.eq(op.oe.oe & op.oe.oe_ok) # OV/32 is to be set
+        with m.If(op.oe.oe & op.oe.oe_ok):
+            comb += self.o.xer_so.data.eq(self.so)
+            comb += self.o.xer_so.ok.eq(1)
+            comb += self.o.xer_ov.data.eq(xer_ov_i)
+            comb += self.o.xer_ov.ok.eq(1) # OV/32 is to be set
 
         return m