format code

[soc.git] / src / soc / fu / alu / pipe_data.py

diff --git a/src/soc/fu/alu/pipe_data.py b/src/soc/fu/alu/pipe_data.py
index 7b1334156c9de77b65a64e4319b03a9386f15a46..1e552ff6f0ed937f06e17295b52574dc776cb409 100644 (file)
--- a/src/soc/fu/alu/pipe_data.py
+++ b/src/soc/fu/alu/pipe_data.py
@@ -3,10 +3,11 @@ from soc.fu.pipe_data import FUBaseData, CommonPipeSpec
 
 
 class ALUInputData(FUBaseData):
-    regspec = [('INT', 'ra', '0:63'), # RA
-               ('INT', 'rb', '0:63'), # RB/immediate
-               ('XER', 'xer_so', '32'), # XER bit 32: SO
-               ('XER', 'xer_ca', '34,45')] # XER bit 34/45: CA/CA32
+    regspec = [('INT', 'ra', '0:63'),  # RA
+               ('INT', 'rb', '0:63'),  # RB/immediate
+               ('XER', 'xer_so', '32'),  # XER bit 32: SO
+               ('XER', 'xer_ca', '34,45')]  # XER bit 34/45: CA/CA32
+
     def __init__(self, pspec):
         super().__init__(pspec, False)
         # convenience
@@ -16,9 +17,10 @@ class ALUInputData(FUBaseData):
 class ALUOutputData(FUBaseData):
     regspec = [('INT', 'o', '0:63'),
                ('CR', 'cr_a', '0:3'),
-               ('XER', 'xer_ca', '34,45'), # bit0: ca, bit1: ca32
-               ('XER', 'xer_ov', '33,44'), # bit0: ov, bit1: ov32
+               ('XER', 'xer_ca', '34,45'),  # bit0: ca, bit1: ca32
+               ('XER', 'xer_ov', '33,44'),  # bit0: ov, bit1: ov32
                ('XER', 'xer_so', '32')]
+
     def __init__(self, pspec):
         super().__init__(pspec, True)
         # convenience