okaaay add a "rdflags" function which obtains the yes/no flags for each register...

[soc.git] / src / soc / fu / alu / pipe_data.py

diff --git a/src/soc/fu/alu/pipe_data.py b/src/soc/fu/alu/pipe_data.py
index cdd5c97a12e0876462caa7c25564ea3a1ca1d23b..33f54b026b95e06860a9f8b6a9a1b2797fdd59ee 100644 (file)
--- a/src/soc/fu/alu/pipe_data.py
+++ b/src/soc/fu/alu/pipe_data.py
@@ -1,4 +1,4 @@
-from nmigen import Signal, Const
+from nmigen import Signal, Const, Cat
 from soc.fu.alu.alu_input_record import CompALUOpSubset
 from soc.fu.pipe_data import IntegerData, CommonPipeSpec
 from ieee754.fpcommon.getop import FPPipeContext
@@ -64,3 +64,7 @@ class ALUOutputData(IntegerData):
 class ALUPipeSpec(CommonPipeSpec):
     regspec = (ALUInputData.regspec, ALUOutputData.regspec)
     opsubsetkls = CompALUOpSubset
+    def rdflags(self, e): # in order of regspec
+        reg1_ok = e.read_reg1.ok # RA
+        reg2_ok = e.read_reg2.ok # RB
+        return Cat(reg1_ok, reg2_ok, 1, 1) # RA RB CA SO