normalise XER regs carry/32 and SO

[soc.git] / src / soc / fu / alu / pipe_data.py

diff --git a/src/soc/fu/alu/pipe_data.py b/src/soc/fu/alu/pipe_data.py
index 744db57a6c9e4678ffe689e7149aa1f04d98761b..0d299ef477e987d466d5e5fcda0e3e6cc836b39a 100644 (file)
--- a/src/soc/fu/alu/pipe_data.py
+++ b/src/soc/fu/alu/pipe_data.py
@@ -25,21 +25,21 @@ class ALUInputData(IntegerData):
         super().__init__(pspec)
         self.a = Signal(64, reset_less=True) # RA
         self.b = Signal(64, reset_less=True) # RB/immediate
-        self.so = Signal(reset_less=True)
-        self.carry_in = Signal(reset_less=True)
+        self.xer_so = Signal(reset_less=True) # XER bit 32: SO
+        self.xer_ca = Signal(2, reset_less=True) # XER bit 34/45: CA/CA32
 
     def __iter__(self):
         yield from super().__iter__()
         yield self.a
         yield self.b
-        yield self.carry_in
-        yield self.so
+        yield self.xer_ca
+        yield self.xer_so
 
     def eq(self, i):
         lst = super().eq(i)
         return lst + [self.a.eq(i.a), self.b.eq(i.b),
-                      self.carry_in.eq(i.carry_in),
-                      self.so.eq(i.so)]
+                      self.xer_ca.eq(i.xer_ca),
+                      self.xer_so.eq(i.xer_so)]
 
 # TODO: ALUIntermediateData which does not have
 # cr0, ov, ov32 in it (because they are generated as outputs by
@@ -51,14 +51,14 @@ class ALUOutputData(IntegerData):
         super().__init__(pspec)
         self.o = Signal(64, reset_less=True, name="stage_o")
         self.cr0 = Data(4, name="cr0")
-        self.xer_co = Data(2, name="xer_co") # bit0: co, bit1: co32
+        self.xer_ca = Data(2, name="xer_co") # bit0: ca, bit1: ca32
         self.xer_ov = Data(2, name="xer_ov") # bit0: ov, bit1: ov32
         self.xer_so = Data(1, name="xer_so")
 
     def __iter__(self):
         yield from super().__iter__()
         yield self.o
-        yield self.xer_co
+        yield self.xer_ca
         yield self.cr0
         yield self.xer_ov
         yield self.xer_so
@@ -66,7 +66,7 @@ class ALUOutputData(IntegerData):
     def eq(self, i):
         lst = super().eq(i)
         return lst + [self.o.eq(i.o),
-                      self.xer_co.eq(i.xer_co),
+                      self.xer_ca.eq(i.xer_ca),
                       self.cr0.eq(i.cr0),
                       self.xer_ov.eq(i.xer_ov), self.xer_so.eq(i.xer_so)]