from nmigen import Module, Signal
from nmigen.back.pysim import Simulator, Delay, Settle
-from nmigen.test.utils import FHDLTestCase
+from nmutil.formaltest import FHDLTestCase
from nmigen.cli import rtlil
import unittest
from soc.decoder.isa.caller import ISACaller, special_sprs
from soc.decoder.power_decoder import (create_pdecode)
from soc.decoder.power_decoder2 import (PowerDecode2)
-from soc.decoder.power_enums import (XER_bits, Function, InternalOp)
+from soc.decoder.power_enums import (XER_bits, Function, InternalOp, CryIn)
from soc.decoder.selectable_int import SelectableInt
from soc.simulator.program import Program
from soc.decoder.isa.all import ISA
+from soc.fu.test.common import TestCase
from soc.fu.alu.pipeline import ALUBasePipe
-from soc.fu.alu.alu_input_record import CompALUOpSubset
from soc.fu.alu.pipe_data import ALUPipeSpec
import random
-class TestCase:
- def __init__(self, program, regs, sprs, name):
- self.program = program
- self.regs = regs
- self.sprs = sprs
- self.name = name
-
-def get_rec_width(rec):
- recwidth = 0
- # Setup random inputs for dut.op
- for p in rec.ports():
- width = p.width
- recwidth += width
- return recwidth
+
+def get_cu_inputs(dec2, sim):
+ """naming (res) must conform to ALUFunctionUnit input regspec
+ """
+ res = {}
+
+ # RA (or RC)
+ reg1_ok = yield dec2.e.read_reg1.ok
+ if reg1_ok:
+ data1 = yield dec2.e.read_reg1.data
+ res['ra'] = sim.gpr(data1).value
+
+ # RB (or immediate)
+ reg2_ok = yield dec2.e.read_reg2.ok
+ if reg2_ok:
+ data2 = yield dec2.e.read_reg2.data
+ res['rb'] = sim.gpr(data2).value
+
+ # XER.ca
+ cry_in = yield dec2.e.input_carry
+ if cry_in == CryIn.CA.value:
+ carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
+ carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
+ res['xer_ca'] = carry | (carry32<<1)
+
+ # XER.so
+ oe = yield dec2.e.oe.data[0] & dec2.e.oe.ok
+ if oe:
+ so = 1 if sim.spr['XER'][XER_bits['SO']] else 0
+ res['xer_so'] = so
+
+ return res
+
+
def set_alu_inputs(alu, dec2, sim):
# TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
# detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
# and place it into data_i.b
- reg3_ok = yield dec2.e.read_reg3.ok
- reg1_ok = yield dec2.e.read_reg1.ok
- assert reg3_ok != reg1_ok
- if reg3_ok:
- data1 = yield dec2.e.read_reg3.data
- data1 = sim.gpr(data1).value
- elif reg1_ok:
- data1 = yield dec2.e.read_reg1.data
- data1 = sim.gpr(data1).value
- else:
- data1 = 0
-
- yield alu.p.data_i.a.eq(data1)
+ inp = yield from get_cu_inputs(dec2, sim)
+ if 'ra' in inp:
+ yield alu.p.data_i.a.eq(inp['ra'])
+ if 'rb' in inp:
+ yield alu.p.data_i.b.eq(inp['rb'])
# If there's an immediate, set the B operand to that
- reg2_ok = yield dec2.e.read_reg2.ok
imm_ok = yield dec2.e.imm_data.imm_ok
if imm_ok:
data2 = yield dec2.e.imm_data.imm
- elif reg2_ok:
- data2 = yield dec2.e.read_reg2.data
- data2 = sim.gpr(data2).value
- else:
- data2 = 0
- yield alu.p.data_i.b.eq(data2)
-
+ yield alu.p.data_i.b.eq(data2)
-
-def set_extra_alu_inputs(alu, dec2, sim):
- carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
- yield alu.p.data_i.carry_in.eq(carry)
- so = 1 if sim.spr['XER'][XER_bits['SO']] else 0
- yield alu.p.data_i.so.eq(so)
+ if 'xer_ca' in inp:
+ yield alu.p.data_i.xer_ca.eq(inp['xer_ca'])
+ print ("extra inputs: CA/32", bin(inp['xer_ca']))
+ if 'xer_so' in inp:
+ so = inp['xer_so']
+ print ("extra inputs: so", so)
+ yield alu.p.data_i.xer_so.eq(so)
# This test bench is a bit different than is usual. Initially when I
# massively. Before, it took around 1 minute on my computer, now it
# takes around 3 seconds
-test_data = []
-
class ALUTestCase(FHDLTestCase):
+ test_data = []
+
def __init__(self, name):
super().__init__(name)
self.test_name = name
- def run_tst_program(self, prog, initial_regs=[0] * 32, initial_sprs={}):
- tc = TestCase(prog, initial_regs, initial_sprs, self.test_name)
- test_data.append(tc)
+ def run_tst_program(self, prog, initial_regs=None, initial_sprs=None):
+ tc = TestCase(prog, self.test_name, initial_regs, initial_sprs)
+ self.test_data.append(tc)
def test_rand(self):
insns = ["add", "add.", "subf"]
self.run_tst_program(Program(lst), initial_regs)
def test_cmpeqb(self):
- lst = ["cmpeqb cr0, 1, 2"]
+ lst = ["cmpeqb cr1, 1, 2"]
for i in range(20):
initial_regs = [0] * 32
initial_regs[1] = i
- initial_regs[2] = 0x01030507090b0d0f11
+ initial_regs[2] = 0x0001030507090b0f
self.run_tst_program(Program(lst), initial_regs, {})
def test_ilang(self):
- rec = CompALUOpSubset()
-
- pspec = ALUPipeSpec(id_wid=2, op_wid=get_rec_width(rec))
+ pspec = ALUPipeSpec(id_wid=2)
alu = ALUBasePipe(pspec)
vl = rtlil.convert(alu, ports=alu.ports())
with open("alu_pipeline.il", "w") as f:
m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
- rec = CompALUOpSubset()
-
- pspec = ALUPipeSpec(id_wid=2, op_wid=get_rec_width(rec))
+ pspec = ALUPipeSpec(id_wid=2)
m.submodules.alu = alu = ALUBasePipe(pspec)
comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.e)
print(test.name)
program = test.program
self.subTest(test.name)
- simulator = ISA(pdecode2, test.regs, test.sprs, 0)
+ simulator = ISA(pdecode2, test.regs, test.sprs, test.cr,
+ test.mem, test.msr)
gen = program.generate_instructions()
instructions = list(zip(gen, program.assembly.splitlines()))
fn_unit = yield pdecode2.e.fn_unit
self.assertEqual(fn_unit, Function.ALU.value)
yield from set_alu_inputs(alu, pdecode2, simulator)
- yield from set_extra_alu_inputs(alu, pdecode2, simulator)
yield
opname = code.split(' ')[0]
yield from simulator.call(opname)
yield
vld = yield alu.n.valid_o
yield
- alu_out = yield alu.n.data_o.o
+ alu_out = yield alu.n.data_o.o.data
out_reg_valid = yield pdecode2.e.write_reg.ok
if out_reg_valid:
write_reg_idx = yield pdecode2.e.write_reg.data
expected = simulator.gpr(write_reg_idx).value
print(f"expected {expected:x}, actual: {alu_out:x}")
- self.assertEqual(expected, alu_out)
+ self.assertEqual(expected, alu_out, code)
yield from self.check_extra_alu_outputs(alu, pdecode2,
simulator, code)
def check_extra_alu_outputs(self, alu, dec2, sim, code):
rc = yield dec2.e.rc.data
+ op = yield dec2.e.insn_type
+ cridx_ok = yield dec2.e.write_cr.ok
+ cridx = yield dec2.e.write_cr.data
+
+ print ("check extra output", repr(code), cridx_ok, cridx)
if rc:
- cr_expected = sim.crl[0].get_range().value
- cr_actual = yield alu.n.data_o.cr0.data
- self.assertEqual(cr_expected, cr_actual, code)
+ self.assertEqual(cridx, 0, code)
- op = yield dec2.e.insn_type
- if op == InternalOp.OP_CMP.value or \
- op == InternalOp.OP_CMPEQB.value:
- bf = yield dec2.dec.BF
+ if cridx_ok:
+ cr_expected = sim.crl[cridx].get_range().value
cr_actual = yield alu.n.data_o.cr0.data
- cr_expected = sim.crl[bf].get_range().value
- self.assertEqual(cr_expected, cr_actual, code)
+ print ("CR", cridx, cr_expected, cr_actual)
+ self.assertEqual(cr_expected, cr_actual, "CR%d %s" % (cridx, code))
cry_out = yield dec2.e.output_carry
if cry_out:
expected_carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
- real_carry = yield alu.n.data_o.xer_co.data[0] # XXX CO not CO32
+ real_carry = yield alu.n.data_o.xer_ca.data[0] # XXX CO not CO32
self.assertEqual(expected_carry, real_carry, code)
expected_carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
- real_carry32 = yield alu.n.data_o.xer_co.data[1] # XXX CO32
- self.assertEqual(expected_carry, real_carry, code)
+ real_carry32 = yield alu.n.data_o.xer_ca.data[1] # XXX CO32
+ self.assertEqual(expected_carry32, real_carry32, code)
if __name__ == "__main__":
unittest.main(exit=False)
suite = unittest.TestSuite()
- suite.addTest(TestRunner(test_data))
+ suite.addTest(TestRunner(ALUTestCase.test_data))
runner = unittest.TextTestRunner()
runner.run(suite)
projects / soc.git / blobdiff