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[soc.git] / src / soc / fu / alu / test / test_pipe_caller.py

diff --git a/src/soc/fu/alu/test/test_pipe_caller.py b/src/soc/fu/alu/test/test_pipe_caller.py
index 88b61b70abbbb302eabc26726b45d2d3a92ae6bd..d914010a82bc1e3bb7f286156dc48b92839e70d8 100644 (file)
--- a/src/soc/fu/alu/test/test_pipe_caller.py
+++ b/src/soc/fu/alu/test/test_pipe_caller.py
@@ -1,8 +1,15 @@
 from nmigen import Module, Signal
 from nmigen.back.pysim import Delay, Settle
+# NOTE: to use this (set to True), at present it is necessary to check
+# out the cxxsim nmigen branch
 cxxsim = False
 if cxxsim:
-    from nmigen.sim.cxxsim import Simulator
+    try:
+        from nmigen.sim.cxxsim import Simulator
+    except ImportError:
+        print("nope, sorry, have to use nmigen cxxsim branch for now")
+        cxxsim = False
+        from nmigen.back.pysim import Simulator
 else:
     from nmigen.back.pysim import Simulator
 
@@ -144,7 +151,8 @@ class ALUTestCase(FHDLTestCase):
             xer = SelectableInt(0, 64)
             xer[XER_bits['CA']] = 1
             initial_sprs[special_sprs['XER']] = xer
-            self.run_tst_program(Program(lst, bigendian), initial_regs, initial_sprs)
+            self.run_tst_program(Program(lst, bigendian),
+                                 initial_regs, initial_sprs)
 
     def test_cmp(self):
         lst = ["subf. 1, 6, 7",
@@ -248,12 +256,8 @@ class TestRunner(FHDLTestCase):
                     yield from self.check_alu_outputs(alu, pdecode2, sim, code)
 
         sim.add_sync_process(process)
-        if cxxsim:
-             sim.run()
-        else:
-            with sim.write_vcd("alu_simulator.vcd", "simulator.gtkw",
-                                traces=[]):
-                sim.run()
+        sim.write_vcd("alu_simulator.vcd")
+        sim.run()
 
     def check_alu_outputs(self, alu, dec2, sim, code):