update mmu testcase

[soc.git] / src / soc / fu / base_input_record.py

diff --git a/src/soc/fu/base_input_record.py b/src/soc/fu/base_input_record.py
index 50c5958bf9fe843f417103447e3b2e8f47927a84..524ad073e18f6c9bffbd23d7cab75c3b82f23a22 100644 (file)
--- a/src/soc/fu/base_input_record.py
+++ b/src/soc/fu/base_input_record.py
@@ -21,17 +21,22 @@ class CompOpSubsetBase(Record):
         for fname, sig in self.fields.items():
             sig.reset_less = True
 
-    def eq_from_execute1(self, other):
-        """ use this to copy in from Decode2Execute1Type
+    def eq_from(self, other):
+        """ use this to copy in from another CompRecord
         """
         res = []
-        print ("eq_from_execute self", self, self.fields)
-        print ("                other", other, other.fields)
+        print ("eq_from self", self, self.fields)
+        print ("        other", other, other.fields)
         for fname, sig in self.fields.items():
-            eqfrom = other.do.fields[fname]
+            eqfrom = other.fields[fname]
             res.append(sig.eq(eqfrom))
         return res
 
+    def eq_from_execute1(self, other):
+        """ use this to copy in from Decode2Execute1Type
+        """
+        return self.eq_from(other)
+
     def ports(self):
         res = []
         for fname, sig in self.fields.items():