whoops was still copying output over in CommonOutputStage

[soc.git] / src / soc / fu / base_input_record.py

diff --git a/src/soc/fu/base_input_record.py b/src/soc/fu/base_input_record.py
index e39daef89a647da3e110ce03d215dfb721fe40b0..99f763bb8c48775eaecbcd5e5729a6d0f5fa8452 100644 (file)
--- a/src/soc/fu/base_input_record.py
+++ b/src/soc/fu/base_input_record.py
@@ -1,6 +1,9 @@
 from nmigen.hdl.rec import Record, Layout
 from nmigen import Signal
 
+# needed for SVP64 information at the pipeline
+from openpower.decoder.power_svp64_rm import sv_input_record_layout
+
 
 class CompOpSubsetBase(Record):
     """CompOpSubsetBase
@@ -15,6 +18,7 @@ class CompOpSubsetBase(Record):
             assert name.endswith("OpSubset")
             name = name[4:-8].lower() + "_op"
 
+        layout = list(layout) + sv_input_record_layout
         Record.__init__(self, Layout(layout), name=name)
 
         # grrr.  Record does not have kwargs
@@ -35,7 +39,7 @@ class CompOpSubsetBase(Record):
     def eq_from_execute1(self, other):
         """ use this to copy in from Decode2Execute1Type
         """
-        return self.eq_from(other.do)
+        return self.eq_from(other)
 
     def ports(self):
         res = []