move over to from openpower imports

[soc.git] / src / soc / fu / branch / formal / proof_input_stage.py

diff --git a/src/soc/fu/branch/formal/proof_input_stage.py b/src/soc/fu/branch/formal/proof_input_stage.py
index 89346e21526ef1f3bd65f6fc9dcef660a5047a27..780fcbeace7c2271492863588dbaf3a45ef9637a 100644 (file)
--- a/src/soc/fu/branch/formal/proof_input_stage.py
+++ b/src/soc/fu/branch/formal/proof_input_stage.py
@@ -9,7 +9,7 @@ from nmigen.cli import rtlil
 from soc.fu.alu.input_stage import ALUInputStage
 from soc.fu.alu.pipe_data import ALUPipeSpec
 from soc.fu.branch.br_input_record import CompBROpSubset
-from soc.decoder.power_enums import MicrOp
+from openpower.decoder.power_enums import MicrOp
 import unittest