fix up Logical pipeline to produce HDL with XLEN=32

[soc.git] / src / soc / fu / branch / main_stage.py

diff --git a/src/soc/fu/branch/main_stage.py b/src/soc/fu/branch/main_stage.py
index 39631afdca281c1b280765281cbae5cb000b35b3..13bd79024ccbad8d7bd9e0aa013fe76f2e5c7f60 100644 (file)
--- a/src/soc/fu/branch/main_stage.py
+++ b/src/soc/fu/branch/main_stage.py
@@ -1,3 +1,7 @@
+# License: LGPLv3
+# Copyright (C) 2020 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+# Copyright (C) 2020 Michael Nolan <mtnolan2640@gmail.com>
+
 """Branch Pipeline
 
 This stage is intended to do most of the work of executing branch
@@ -28,10 +32,10 @@ from nmigen import (Module, Signal, Cat, Mux, Const, Array)
 from nmutil.pipemodbase import PipeModBase
 from nmutil.extend import exts
 from soc.fu.branch.pipe_data import BranchInputData, BranchOutputData
-from soc.decoder.power_enums import MicrOp
+from openpower.decoder.power_enums import MicrOp
 
-from soc.decoder.power_fields import DecodeFields
-from soc.decoder.power_fieldsn import SignalBitRange
+from openpower.decoder.power_fields import DecodeFields
+from openpower.decoder.power_fieldsn import SignalBitRange
 
 
 def br_ext(bd):
@@ -92,11 +96,15 @@ class BranchMainStage(PipeModBase):
 
         # fields for conditional branches (BO and BI are same for BC and BCREG)
         b_fields = self.fields.FormB
-        BO = b_fields.BO[0:-1]
-        BI = b_fields.BI[0:-1][0:2] # CR0-7 selected already in PowerDecode2.
+        BO = b_fields.BO
+        BI = b_fields.BI[0:2] # CR0-7 selected already in PowerDecode2.
 
         cr_bits = Array([cr[3-i] for i in range(4)]) # invert. Because POWER.
 
+        # copy of BO in a signal
+        bo = Signal(5, reset_less=True)
+        comb += bo.eq(BO[0:5])
+
         # The bit of CR selected by BI
         bi = Signal(2, reset_less=True)
         cr_bit = Signal(reset_less=True)
@@ -109,8 +117,8 @@ class BranchMainStage(PipeModBase):
 
         # Whether the conditional branch should be taken
         bc_taken = Signal(reset_less=True)
-        with m.If(BO[2]):
-            comb += bc_taken.eq((cr_bit == BO[3]) | BO[4])
+        with m.If(bo[2]):
+            comb += bc_taken.eq((cr_bit == bo[3]) | bo[4])
         with m.Else():
             # decrement the counter and place into output
             ctr_n = Signal(64, reset_less=True)
@@ -123,14 +131,14 @@ class BranchMainStage(PipeModBase):
                 comb += ctr_m.eq(ctr[:32])
             with m.Else():
                 comb += ctr_m.eq(ctr)
-            # check CTR zero/non-zero against BO[1]
-            ctr_zero_bo1 = Signal(reset_less=True) # BO[1] == (ctr==0)
-            comb += ctr_zero_bo1.eq(BO[1] ^ ctr_m.any())
-            with m.If(BO[3:5] == 0b00):
+            # check CTR zero/non-zero against bo[1]
+            ctr_zero_bo1 = Signal(reset_less=True) # bo[1] == (ctr==0)
+            comb += ctr_zero_bo1.eq(bo[1] ^ ctr_n.any())
+            with m.If(bo[3:5] == 0b00):
                 comb += bc_taken.eq(ctr_zero_bo1 & ~cr_bit)
-            with m.Elif(BO[3:5] == 0b01):
+            with m.Elif(bo[3:5] == 0b01):
                 comb += bc_taken.eq(ctr_zero_bo1 & cr_bit)
-            with m.Elif(BO[4] == 1):
+            with m.Elif(bo[4] == 1):
                 comb += bc_taken.eq(ctr_zero_bo1)
 
         ### Main Switch Statement ###