from nmigen import Module, Signal
from nmigen.back.pysim import Simulator, Delay, Settle
-from nmigen.test.utils import FHDLTestCase
from nmigen.cli import rtlil
import unittest
from soc.decoder.isa.caller import ISACaller, special_sprs
from soc.decoder.power_decoder import (create_pdecode)
from soc.decoder.power_decoder2 import (PowerDecode2)
-from soc.decoder.power_enums import (XER_bits, Function)
+from soc.decoder.power_enums import (XER_bits, Function, MicrOp)
from soc.decoder.selectable_int import SelectableInt
from soc.simulator.program import Program
from soc.decoder.isa.all import ISA
from soc.regfile.regfiles import FastRegs
+from soc.config.endian import bigendian
+from soc.fu.test.common import TestAccumulatorBase, TestCase, ALUHelpers
from soc.fu.branch.pipeline import BranchBasePipe
from soc.fu.branch.pipe_data import BranchPipeSpec
import random
+from soc.regfile.util import fast_reg_to_spr # HACK!
-class TestCase:
- def __init__(self, program, regs, sprs, cr, name):
- self.program = program
- self.regs = regs
- self.sprs = sprs
- self.name = name
- self.cr = cr
def get_rec_width(rec):
recwidth = 0
# massively. Before, it took around 1 minute on my computer, now it
# takes around 3 seconds
-test_data = []
+def get_cu_inputs(dec2, sim):
+ """naming (res) must conform to BranchFunctionUnit input regspec
+ """
+ res = {}
-class BranchTestCase(FHDLTestCase):
- def __init__(self, name):
- super().__init__(name)
- self.test_name = name
- def run_tst_program(self, prog, initial_regs=[0] * 32,
- initial_sprs={}, initial_cr=0):
- tc = TestCase(prog, initial_regs, initial_sprs, initial_cr,
- self.test_name)
- test_data.append(tc)
+ # CIA (PC)
+ #res['cia'] = sim.pc.CIA.value
- def test_unconditional(self):
+ yield from ALUHelpers.get_sim_fast_spr1(res, sim, dec2)
+ yield from ALUHelpers.get_sim_fast_spr2(res, sim, dec2)
+ yield from ALUHelpers.get_sim_cr_a(res, sim, dec2)
+
+ print("get inputs", res)
+ return res
+
+
+class BranchTestCase(TestAccumulatorBase):
+
+ def case_0_regression_unconditional(self):
+ for i in range(2):
+ imm = random.randrange(-1 << 23, (1 << 23)-1) * 4
+ lst = [f"bl {imm}"]
+ initial_regs = [0] * 32
+ self.add_case(Program(lst, bigendian), initial_regs)
+
+ def case_unconditional(self):
choices = ["b", "ba", "bl", "bla"]
for i in range(20):
choice = random.choice(choices)
- imm = random.randrange(-1<<23, (1<<23)-1) * 4
+ imm = random.randrange(-1 << 23, (1 << 23)-1) * 4
lst = [f"{choice} {imm}"]
initial_regs = [0] * 32
- self.run_tst_program(Program(lst), initial_regs)
+ self.add_case(Program(lst, bigendian), initial_regs)
- def test_bc_cr(self):
+ def case_bc_cr(self):
for i in range(20):
- bc = random.randrange(-1<<13, (1<<13)-1) * 4
+ bc = random.randrange(-1 << 13, (1 << 13)-1) * 4
bo = random.choice([0b01100, 0b00100, 0b10100])
bi = random.randrange(0, 31)
- cr = random.randrange(0, (1<<32)-1)
+ cr = random.randrange(0, (1 << 32)-1)
lst = [f"bc {bo}, {bi}, {bc}"]
initial_regs = [0] * 32
- self.run_tst_program(Program(lst), initial_cr=cr)
+ self.add_case(Program(lst, bigendian), initial_cr=cr)
- def test_bc_ctr(self):
+ def case_bc_ctr(self):
for i in range(20):
- bc = random.randrange(-1<<13, (1<<13)-1) * 4
+ bc = random.randrange(-1 << 13, (1 << 13)-1) * 4
bo = random.choice([0, 2, 8, 10, 16, 18])
bi = random.randrange(0, 31)
- cr = random.randrange(0, (1<<32)-1)
- ctr = random.randint(0, (1<<32)-1)
+ cr = random.randrange(0, (1 << 32)-1)
+ ctr = random.randint(0, (1 << 32)-1)
lst = [f"bc {bo}, {bi}, {bc}"]
- initial_sprs={9: SelectableInt(ctr, 64)}
- self.run_tst_program(Program(lst),
+ initial_sprs = {9: SelectableInt(ctr, 64)}
+ self.add_case(Program(lst, bigendian),
initial_sprs=initial_sprs,
initial_cr=cr)
- def test_bc_reg(self):
+ def case_bc_reg(self):
# XXX: bcctr and bcctrl time out (irony: they're counters)
- choices = ["bclr", "bclrl", "bcctr", "bcctrl"]
+ choices = ["bclr", "bclrl", "bcctr", "bcctrl", "bctar", "bctarl"]
for insn in choices:
for i in range(20):
bh = random.randrange(0, 3)
bo = random.choice([4, 12])
bi = random.randrange(0, 31)
- cr = random.randrange(0, (1<<32)-1)
- ctr = random.randint(0, (1<<32)-1)
+ cr = random.randrange(0, (1 << 32)-1)
+ ctr = random.randint(0, (1 << 32)-1)
+ lr = random.randint(0, (1 << 64)-1) & ~3
+ tar = random.randint(0, (1 << 64)-1) & ~3
lst = [f"{insn} {bo}, {bi}, {bh}"]
- initial_sprs={9: SelectableInt(ctr, 64)}
- self.run_tst_program(Program(lst),
+ initial_sprs = {9: SelectableInt(ctr, 64),
+ 8: SelectableInt(lr, 64),
+ 815: SelectableInt(tar, 64)}
+ self.add_case(Program(lst, bigendian),
initial_sprs=initial_sprs,
initial_cr=cr)
-
-
- def test_ilang(self):
+ def case_ilang(self):
pspec = BranchPipeSpec(id_wid=2)
alu = BranchBasePipe(pspec)
vl = rtlil.convert(alu, ports=alu.ports())
f.write(vl)
-class TestRunner(FHDLTestCase):
+class TestRunner(unittest.TestCase):
def __init__(self, test_data):
super().__init__("run_all")
self.test_data = test_data
sim = Simulator(m)
sim.add_clock(1e-6)
+
def process():
for test in self.test_data:
print(test.name)
program = test.program
self.subTest(test.name)
- simulator = ISA(pdecode2, test.regs, test.sprs, test.cr)
+ simulator = ISA(pdecode2, test.regs, test.sprs, test.cr,
+ test.mem, test.msr,
+ bigendian=bigendian)
initial_cia = 0x2000
simulator.set_pc(initial_cia)
gen = program.generate_instructions()
instructions = list(zip(gen, program.assembly.splitlines()))
- index = (simulator.pc.CIA.value - initial_cia)//4
+ pc = simulator.pc.CIA.value
+ msr = simulator.msr.value
+ index = (pc - initial_cia)//4
while index < len(instructions) and index >= 0:
print(index)
ins, code = instructions[index]
print(code)
# ask the decoder to decode this binary data (endian'd)
- yield pdecode2.dec.bigendian.eq(0) # little / big?
+ yield pdecode2.dec.bigendian.eq(bigendian) # little / big?
+ yield pdecode2.msr.eq(msr) # set MSR in pdecode2
+ yield pdecode2.cia.eq(pc) # set PC in pdecode2
yield instruction.eq(ins) # raw binary instr.
- yield branch.p.data_i.cia.eq(simulator.pc.CIA.value)
# note, here, the op will need further decoding in order
# to set the correct SPRs on SPR1/2/3. op_bc* require
# spr1 to be set to CTR, op_bctar require spr2 to be
# if op_sc*, op_rf* and op_hrfid are to be added here
# then additional op-decoding is required, accordingly
yield Settle()
+ lk = yield pdecode2.e.do.lk
+ print("lk:", lk)
yield from self.set_inputs(branch, pdecode2, simulator)
- fn_unit = yield pdecode2.e.fn_unit
+ fn_unit = yield pdecode2.e.do.fn_unit
self.assertEqual(fn_unit, Function.BRANCH.value, code)
yield
yield
opname = code.split(' ')[0]
prev_nia = simulator.pc.NIA.value
yield from simulator.call(opname)
- index = (simulator.pc.CIA.value - initial_cia)//4
+ pc = simulator.pc.CIA.value
+ msr = simulator.msr.value
+ index = (pc - initial_cia)//4
yield from self.assert_outputs(branch, pdecode2,
simulator, prev_nia, code)
sim.add_sync_process(process)
- with sim.write_vcd("simulator.vcd", "simulator.gtkw",
- traces=[]):
+ with sim.write_vcd("branch_simulator.vcd"):
sim.run()
def assert_outputs(self, branch, dec2, sim, prev_nia, code):
print(f"real: {branch_addr:x}, sim: {sim.pc.CIA.value:x}")
self.assertEqual(branch_addr, sim.pc.CIA.value, code)
- lk = yield dec2.e.lk
+ # TODO: check write_fast1 as well (should contain CTR)
+
+ # TODO: this should be checking write_fast2
+ lk = yield dec2.e.do.lk
branch_lk = yield branch.n.data_o.lr.ok
self.assertEqual(lk, branch_lk, code)
if lk:
self.assertEqual(sim.spr['LR'], branch_lr, code)
def set_inputs(self, branch, dec2, sim):
- yield branch.p.data_i.spr1.eq(sim.spr['CTR'].value)
print(f"cr0: {sim.crl[0].get_range()}")
- # TODO: this needs to now be read_fast1.data and read_fast2.data
-
- spr2_en = yield dec2.e.read_spr2.ok
- if spr2_en:
- spr2_sel = yield dec2.e.read_spr2.data
- if spr2_sel == FastRegs.LR:
- spr2_data = sim.spr['LR'].value
- elif spr2_sel == FastRegs.CTR:
- spr2_data = sim.spr['CTR'].value
- yield branch.p.data_i.spr2.eq(spr2_data)
+ inp = yield from get_cu_inputs(dec2, sim)
- cr_en = yield dec2.e.read_cr1.ok
- if cr_en:
- cr_sel = yield dec2.e.read_cr1.data
- cr = sim.crl[cr_sel].get_range().value
- yield branch.p.data_i.cr.eq(cr)
- full_cr = sim.cr.get_range().value
- print(f"full cr: {full_cr:x}, sel: {cr_sel}, cr: {cr:x}")
+ yield from ALUHelpers.set_fast_spr1(branch, dec2, inp)
+ yield from ALUHelpers.set_fast_spr2(branch, dec2, inp)
+ yield from ALUHelpers.set_cr_a(branch, dec2, inp)
if __name__ == "__main__":
unittest.main(exit=False)
suite = unittest.TestSuite()
- suite.addTest(TestRunner(test_data))
+ suite.addTest(TestRunner(BranchTestCase().test_data))
runner = unittest.TextTestRunner()
runner.run(suite)
projects / soc.git / blobdiff