from soc.decoder.isa.caller import ISACaller, special_sprs
from soc.decoder.power_decoder import (create_pdecode)
from soc.decoder.power_decoder2 import (PowerDecode2)
-from soc.decoder.power_enums import (XER_bits, Function)
+from soc.decoder.power_enums import (XER_bits, Function, InternalOp)
from soc.decoder.selectable_int import SelectableInt
from soc.simulator.program import Program
from soc.decoder.isa.all import ISA
+from soc.regfile.regfiles import FastRegs
-
-from soc.branch.pipeline import BranchBasePipe
-from soc.branch.br_input_record import CompBROpSubset
-from soc.alu.pipe_data import ALUPipeSpec
+from soc.fu.branch.pipeline import BranchBasePipe
+from soc.fu.branch.pipe_data import BranchPipeSpec
import random
+from soc.regfile.util import fast_reg_to_spr # HACK!
class TestCase:
def __init__(self, program, regs, sprs, cr, name):
initial_sprs=initial_sprs,
initial_cr=cr)
- def test_ilang(self):
- rec = CompBROpSubset()
+ def test_bc_reg(self):
+ # XXX: bcctr and bcctrl time out (irony: they're counters)
+ choices = ["bclr", "bclrl", "bcctr", "bcctrl", "bctar", "bctarl"]
+ for insn in choices:
+ for i in range(20):
+ bh = random.randrange(0, 3)
+ bo = random.choice([4, 12])
+ bi = random.randrange(0, 31)
+ cr = random.randrange(0, (1<<32)-1)
+ ctr = random.randint(0, (1<<32)-1)
+ lr = random.randint(0, (1<<64)-1) & ~3
+ tar = random.randint(0, (1<<64)-1) & ~3
+ lst = [f"{insn} {bo}, {bi}, {bh}"]
+ initial_sprs={9: SelectableInt(ctr, 64),
+ 8: SelectableInt(lr, 64),
+ 815: SelectableInt(tar, 64)}
+ self.run_tst_program(Program(lst),
+ initial_sprs=initial_sprs,
+ initial_cr=cr)
+
+
- pspec = ALUPipeSpec(id_wid=2, op_wid=get_rec_width(rec))
+ def test_ilang(self):
+ pspec = BranchPipeSpec(id_wid=2)
alu = BranchBasePipe(pspec)
vl = rtlil.convert(alu, ports=alu.ports())
- with open("logical_pipeline.il", "w") as f:
+ with open("branch_pipeline.il", "w") as f:
f.write(vl)
m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
- rec = CompBROpSubset()
-
- pspec = ALUPipeSpec(id_wid=2, op_wid=get_rec_width(rec))
+ pspec = BranchPipeSpec(id_wid=2)
m.submodules.branch = branch = BranchBasePipe(pspec)
comb += branch.p.data_i.ctx.op.eq_from_execute1(pdecode2.e)
yield pdecode2.dec.bigendian.eq(0) # little / big?
yield instruction.eq(ins) # raw binary instr.
yield branch.p.data_i.cia.eq(simulator.pc.CIA.value)
- yield branch.p.data_i.cr.eq(simulator.cr.get_range().value)
# note, here, the op will need further decoding in order
# to set the correct SPRs on SPR1/2/3. op_bc* require
- # spr2 to be set to CTR, op_bctar require spr1 to be
- # set to TAR, op_bclr* require spr1 to be set to LR.
+ # spr1 to be set to CTR, op_bctar require spr2 to be
+ # set to TAR, op_bclr* require spr2 to be set to LR.
# if op_sc*, op_rf* and op_hrfid are to be added here
# then additional op-decoding is required, accordingly
- yield branch.p.data_i.spr2.eq(simulator.spr['CTR'].value)
- print(f"cr0: {simulator.crl[0].get_range()}")
yield Settle()
+ yield from self.set_inputs(branch, pdecode2, simulator)
fn_unit = yield pdecode2.e.fn_unit
self.assertEqual(fn_unit, Function.BRANCH.value, code)
yield
yield from self.assert_outputs(branch, pdecode2,
simulator, prev_nia, code)
-
sim.add_sync_process(process)
with sim.write_vcd("simulator.vcd", "simulator.gtkw",
traces=[]):
self.assertEqual(branch_taken, sim_branch_taken, code)
if branch_taken:
branch_addr = yield branch.n.data_o.nia.data
+ print(f"real: {branch_addr:x}, sim: {sim.pc.CIA.value:x}")
self.assertEqual(branch_addr, sim.pc.CIA.value, code)
+ # TODO: check write_fast1 as well (should contain CTR)
+
+ # TODO: this should be checking write_fast2
lk = yield dec2.e.lk
branch_lk = yield branch.n.data_o.lr.ok
self.assertEqual(lk, branch_lk, code)
branch_lr = yield branch.n.data_o.lr.data
self.assertEqual(sim.spr['LR'], branch_lr, code)
+ def set_inputs(self, branch, dec2, sim):
+ yield branch.p.data_i.spr1.eq(sim.spr['CTR'].value)
+ print(f"cr0: {sim.crl[0].get_range()}")
+
+ # TODO: this needs to now be read_fast1.data and read_fast2.data
+ if False:
+ fast1_en = yield dec2.e.read_fast1.ok
+ if fast1_en:
+ fast1_sel = yield dec2.e.read_fast1.data
+ spr1_sel = fast_reg_to_spr(fast1_sel)
+ spr1_data = sim.spr[spr1_sel].value
+ yield branch.p.data_i.spr1.eq(spr1_data)
+
+ fast2_en = yield dec2.e.read_fast2.ok
+ if fast2_en:
+ fast2_sel = yield dec2.e.read_fast2.data
+ spr2_sel = fast_reg_to_spr(fast2_sel)
+ spr2_data = sim.spr[spr2_sel].value
+ yield branch.p.data_i.spr2.eq(spr2_data)
+
+ # TODO: drop this once it's in PowerDecode2
+ # (actually, DecodeA and DecodeB)
+ insn_type = yield dec2.e.insn_type
+ if insn_type == InternalOp.OP_BCREG.value:
+ xo9 = yield dec2.dec.FormXL.XO[9]
+ xo5 = yield dec2.dec.FormXL.XO[5]
+ if xo9 == 0:
+ yield branch.p.data_i.spr2.eq(sim.spr['LR'].value)
+ elif xo5 == 1:
+ yield branch.p.data_i.spr2.eq(sim.spr['TAR'].value)
+ else:
+ yield branch.p.data_i.spr2.eq(sim.spr['CTR'].value)
+
+ cr_en = yield dec2.e.read_cr1.ok
+ if cr_en:
+ cr_sel = yield dec2.e.read_cr1.data
+ cr = sim.crl[cr_sel].get_range().value
+ yield branch.p.data_i.cr.eq(cr)
+ full_cr = sim.cr.get_range().value
+ print(f"full cr: {full_cr:x}, sel: {cr_sel}, cr: {cr:x}")
+
if __name__ == "__main__":
unittest.main(exit=False)
projects / soc.git / blobdiff