move more files to openpower-isa

[soc.git] / src / soc / fu / branch / test / test_pipe_caller.py

diff --git a/src/soc/fu/branch/test/test_pipe_caller.py b/src/soc/fu/branch/test/test_pipe_caller.py
index c74304450b7a1cf05933815494c13f51d3441157..f68374d13f423e02cda9c2d4bc94615b377bc270 100644 (file)
--- a/src/soc/fu/branch/test/test_pipe_caller.py
+++ b/src/soc/fu/branch/test/test_pipe_caller.py
@@ -1,14 +1,18 @@
 from nmigen import Module, Signal
-from nmigen.back.pysim import Simulator, Delay, Settle
+
+# NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
+# Also, check out the cxxsim nmigen branch, and latest yosys from git
+from nmutil.sim_tmp_alternative import Simulator, Settle
+
 from nmigen.cli import rtlil
 import unittest
-from soc.decoder.isa.caller import ISACaller, special_sprs
-from soc.decoder.power_decoder import (create_pdecode)
-from soc.decoder.power_decoder2 import (PowerDecode2)
-from soc.decoder.power_enums import (XER_bits, Function, MicrOp)
-from soc.decoder.selectable_int import SelectableInt
-from soc.simulator.program import Program
-from soc.decoder.isa.all import ISA
+from openpower.decoder.isa.caller import ISACaller, special_sprs
+from openpower.decoder.power_decoder import (create_pdecode)
+from openpower.decoder.power_decoder2 import (PowerDecode2)
+from openpower.decoder.power_enums import (XER_bits, Function, MicrOp)
+from openpower.decoder.selectable_int import SelectableInt
+from openpower.simulator.program import Program
+from openpower.decoder.isa.all import ISA
 from soc.regfile.regfiles import FastRegs
 from soc.config.endian import bigendian
 
@@ -17,8 +21,6 @@ from soc.fu.branch.pipeline import BranchBasePipe
 from soc.fu.branch.pipe_data import BranchPipeSpec
 import random
 
-from soc.regfile.util import fast_reg_to_spr  # HACK!
-
 
 def get_rec_width(rec):
     recwidth = 0
@@ -154,7 +156,7 @@ class TestRunner(unittest.TestCase):
         pspec = BranchPipeSpec(id_wid=2)
         m.submodules.branch = branch = BranchBasePipe(pspec)
 
-        comb += branch.p.data_i.ctx.op.eq_from_execute1(pdecode2.e)
+        comb += branch.p.data_i.ctx.op.eq_from_execute1(pdecode2.do)
         comb += branch.p.valid_i.eq(1)
         comb += branch.n.ready_i.eq(1)
         comb += pdecode2.dec.raw_opcode_in.eq(instruction)
@@ -214,7 +216,8 @@ class TestRunner(unittest.TestCase):
                         index = (pc - initial_cia)//4
 
                         yield from self.assert_outputs(branch, pdecode2,
-                                                       simulator, prev_nia, code)
+                                                       simulator, prev_nia,
+                                                       code)
 
         sim.add_sync_process(process)
         with sim.write_vcd("branch_simulator.vcd"):