rename invert_a to invert_in because logical inverts RB

[soc.git] / src / soc / fu / common_input_stage.py

diff --git a/src/soc/fu/common_input_stage.py b/src/soc/fu/common_input_stage.py
index 1b64e5ce295342b760564d7764cd511192bbda85..238c8d57a9dec7907d497701597f01e419d90ebb 100644 (file)
--- a/src/soc/fu/common_input_stage.py
+++ b/src/soc/fu/common_input_stage.py
@@ -23,8 +23,8 @@ class CommonInputStage(PipeModBase):
         if hasattr(self, "invert_op"):
             op_to_invert = self.invert_op
 
-        if hasattr(op, "invert_a") and op_to_invert == 'ra':
-            with m.If(op.invert_a):
+        if hasattr(op, "invert_in") and op_to_invert == 'ra':
+            with m.If(op.invert_in):
                 comb += a.eq(~self.i.a)
             with m.Else():
                 comb += a.eq(self.i.a)
@@ -38,8 +38,8 @@ class CommonInputStage(PipeModBase):
         # operand b to be as-is or inverted
         b = Signal.like(self.i.b)
 
-        if hasattr(op, "invert_a") and op_to_invert == 'rb':
-            with m.If(op.invert_a):
+        if hasattr(op, "invert_in") and op_to_invert == 'rb':
+            with m.If(op.invert_in):
                 comb += b.eq(~self.i.b)
             with m.Else():
                 comb += b.eq(self.i.b)