reorg of SO handling related to CR0

[soc.git] / src / soc / fu / common_input_stage.py

diff --git a/src/soc/fu/common_input_stage.py b/src/soc/fu/common_input_stage.py
index 238c8d57a9dec7907d497701597f01e419d90ebb..e36b14db340905cdf097cd084f1f3e9a0a6ca007 100644 (file)
--- a/src/soc/fu/common_input_stage.py
+++ b/src/soc/fu/common_input_stage.py
@@ -66,8 +66,7 @@ class CommonInputStage(PipeModBase):
         ##### sticky overflow and context (both pass-through) #####
 
         if hasattr(self.o, "xer_so"): # hack (for now - for LogicalInputData)
-            with m.If(op.oe.oe_ok):
-                comb += self.o.xer_so.eq(self.i.xer_so)
+            comb += self.o.xer_so.eq(self.i.xer_so)
         comb += self.o.ctx.eq(self.i.ctx)
 
         return m