mmu/fsm: test case for mtspr

[soc.git] / src / soc / fu / common_input_stage.py

diff --git a/src/soc/fu/common_input_stage.py b/src/soc/fu/common_input_stage.py
index 1b64e5ce295342b760564d7764cd511192bbda85..e36b14db340905cdf097cd084f1f3e9a0a6ca007 100644 (file)
--- a/src/soc/fu/common_input_stage.py
+++ b/src/soc/fu/common_input_stage.py
@@ -23,8 +23,8 @@ class CommonInputStage(PipeModBase):
         if hasattr(self, "invert_op"):
             op_to_invert = self.invert_op
 
-        if hasattr(op, "invert_a") and op_to_invert == 'ra':
-            with m.If(op.invert_a):
+        if hasattr(op, "invert_in") and op_to_invert == 'ra':
+            with m.If(op.invert_in):
                 comb += a.eq(~self.i.a)
             with m.Else():
                 comb += a.eq(self.i.a)
@@ -38,8 +38,8 @@ class CommonInputStage(PipeModBase):
         # operand b to be as-is or inverted
         b = Signal.like(self.i.b)
 
-        if hasattr(op, "invert_a") and op_to_invert == 'rb':
-            with m.If(op.invert_a):
+        if hasattr(op, "invert_in") and op_to_invert == 'rb':
+            with m.If(op.invert_in):
                 comb += b.eq(~self.i.b)
             with m.Else():
                 comb += b.eq(self.i.b)
@@ -66,8 +66,7 @@ class CommonInputStage(PipeModBase):
         ##### sticky overflow and context (both pass-through) #####
 
         if hasattr(self.o, "xer_so"): # hack (for now - for LogicalInputData)
-            with m.If(op.oe.oe_ok):
-                comb += self.o.xer_so.eq(self.i.xer_so)
+            comb += self.o.xer_so.eq(self.i.xer_so)
         comb += self.o.ctx.eq(self.i.ctx)
 
         return m